Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85103?usp=email )
Change subject: soc/intel/alderlake: Support early Sign of Life for CSE FW Sync ......................................................................
soc/intel/alderlake: Support early Sign of Life for CSE FW Sync
This will ensure that the user is informed about an ongoing CSE FW Sync.
BUG=b:378458829 TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed during CSE FW Sync.
Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/alderlake/romstage/ux.h 2 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85103/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3acd2fd..9c60ba4 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -182,8 +182,12 @@ if (!CONFIG(INTEL_TXT)) disable_intel_txt();
- if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { + cse_fill_bp_info(); + if (CONFIG(CHROMEOS_ENABLE_ESOL) && is_cse_fw_update_required()) + ux_inform_user_of_update_operation("CSE update"); cse_fw_sync(); + }
/* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h index e7e1d99..14c10e7 100644 --- a/src/soc/intel/alderlake/romstage/ux.h +++ b/src/soc/intel/alderlake/romstage/ux.h @@ -1,3 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ +#define _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ + bool ux_inform_user_of_update_operation(const char *name); + +#endif /* _SOC_INTEL_ALDERLAKE_ROMSTAGE_UX_H_ */