Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
mb/asrock/b85m_pro4: Expand Super I/O comments
Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42399/1
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 98a2ee8..0655a32 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -60,18 +60,18 @@ io 0x60 = 0x0378 irq 0x70 = 6 drq 0x74 = 2 - irq 0xf0 = 0x3b + irq 0xf0 = 0x3b # + ECP and EPP 1.9 end device pnp 2e.2 on # UART A io 0x60 = 0x03f8 irq 0x70 = 4 end device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # PS/2 KBC + device pnp 2e.5 on # PS/2 Keyboard/Mouse io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 1 # + Keyboard - irq 0x72 = 12 # + Mouse + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO8 @@ -100,8 +100,8 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 - io 0x60 = 0x0290 + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG@8 PS2, Line 8: + denotes IRQ settings?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG@8 PS2, Line 8:
- denotes IRQ settings?
"+" is what I used there to indent the comments that are about registers. I've no idea why I used a plus sign.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42399/2//COMMIT_MSG@8 PS2, Line 8:
"+" is what I used there to indent the comments that are about registers. […]
Ack
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... PS10, Line 103: irq 0x30 = 0xe1 # + Fan RPM sense pins haven't looked at the datasheet, but this seems weird to me. 0x30 is the LDN/virtual LDN enable register
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... PS10, Line 103: irq 0x30 = 0xe1 # + Fan RPM sense pins
haven't looked at the datasheet, but this seems weird to me. […]
On that particular SIO, it also works to select where fan RPM sense pins are located
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... PS10, Line 103: irq 0x30 = 0xe1 # + Fan RPM sense pins
On that particular SIO, it also works to select where fan RPM sense pins are located
eww. did you check if this results in the right value ending up the the register?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... PS10, Line 103: irq 0x30 = 0xe1 # + Fan RPM sense pins
eww. […]
Looks like it does.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... File src/mainboard/asrock/b85m_pro4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42399/10/src/mainboard/asrock/b85m_... PS10, Line 103: irq 0x30 = 0xe1 # + Fan RPM sense pins
Looks like it does.
ok
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42399 )
Change subject: mb/asrock/b85m_pro4: Expand Super I/O comments ......................................................................
mb/asrock/b85m_pro4: Expand Super I/O comments
Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42399 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 98a2ee8..0655a32 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -60,18 +60,18 @@ io 0x60 = 0x0378 irq 0x70 = 6 drq 0x74 = 2 - irq 0xf0 = 0x3b + irq 0xf0 = 0x3b # + ECP and EPP 1.9 end device pnp 2e.2 on # UART A io 0x60 = 0x03f8 irq 0x70 = 4 end device pnp 2e.3 off end # UART B, IR - device pnp 2e.5 on # PS/2 KBC + device pnp 2e.5 on # PS/2 Keyboard/Mouse io 0x60 = 0x0060 io 0x62 = 0x0064 - irq 0x70 = 1 # + Keyboard - irq 0x72 = 12 # + Mouse + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) end device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO8 @@ -100,8 +100,8 @@ irq 0xf0 = 0x20 end device pnp 2e.b on # HWM, LED - irq 0x30 = 0xe1 - io 0x60 = 0x0290 + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up