Change in coreboot[master]: mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27905

Change subject: mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U
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mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U

Coffeelake U has 32MB flash chip support. Adding fmd file and enabling
CFL U board's Kconfig to output 32MB rom file.

Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc
Signed-off-by: Maulik V Vaghela 
---
M src/mainboard/intel/coffeelake_rvp/Kconfig
A src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
2 files changed, 45 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/27905/1

diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 9dcb02c..bd6eef9 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -2,7 +2,8 @@

config BOARD_SPECIFIC_OPTIONS
    def_bool y
-	select BOARD_ROMSIZE_KB_16384
+	select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU
+	select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU
    select GENERIC_SPD_BIN
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
new file mode 100644
index 0000000..be6bfc0
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
@@ -0,0 +1,43 @@
+FLASH@0xfe000000 0x2000000 {
+	SI_ALL@0x0 0x1081000 {
+		SI_DESC@0x0 0x1000
+		SI_EC@0x1000 0x80000
+		SI_ME@0x81000 0x1000000
+	}
+	SI_BIOS@0x1400000 0xC00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD@0x28000 0x2000
+			RW_NVRAM@0x2a000 0x6000
+		}
+		RW_LEGACY(CBFS)@0x5d0000 0x200000
+		WP_RO@0x7d0000 0x430000 {
+			RO_VPD@0x0 0x4000
+			RO_SECTION@0x4000 0x42c000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x33c000
+			}
+		}
+	}
+}