Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30813
to review the following change.
Change subject: cpu/intel/car/non-evict: Update microcode in CAR setup ......................................................................
cpu/intel/car/non-evict: Update microcode in CAR setup
On CPU's with a non eviction mode we cache the whole ROM to speed up finding the microcode updates, remove the caching to fill in the non eviction mode and then turn on caching the whole ROM again to speed executing XIP code in flash.
Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 36 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30813/1
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4ac6d29..d2beaa7 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -114,6 +114,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr
+ /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25)
/* Enable MTRR. */ @@ -128,6 +139,30 @@ invd movl %eax, %cr0
+#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + /* Disable caching to change MTRR's. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* Clear the mask valid to disable the MTRR */ + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + andl $(~MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + /* enable the 'no eviction' mode */ movl $NoEvictMod_MSR, %ecx rdmsr @@ -154,15 +189,9 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0
- /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
post_code(0x28)
Hello Patrick Rudolph, Arthur Heymans, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30813
to look at the new patch set (#3).
Change subject: cpu/intel/car/non-evict: Update microcode in CAR setup ......................................................................
cpu/intel/car/non-evict: Update microcode in CAR setup
On CPU's with a non eviction mode we cache the whole ROM to speed up finding the microcode updates, remove the caching to fill in the non eviction mode and then turn on caching the whole ROM again to speed executing XIP code in flash.
Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/30682 --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 36 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30813/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30813 )
Change subject: cpu/intel/car/non-evict: Update microcode in CAR setup ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30813 )
Change subject: cpu/intel/car/non-evict: Update microcode in CAR setup ......................................................................
cpu/intel/car/non-evict: Update microcode in CAR setup
On CPU's with a non eviction mode we cache the whole ROM to speed up finding the microcode updates, remove the caching to fill in the non eviction mode and then turn on caching the whole ROM again to speed executing XIP code in flash.
Change-Id: Ib7f36678913e0ba8ef1305bca2c482f375b23eaf Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/30682 Reviewed-on: https://review.coreboot.org/c/30813 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/car/non-evict/cache_as_ram.S 1 file changed, 36 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4ac6d29..d2beaa7 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -114,6 +114,17 @@ movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr
+ /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRR_PHYS_BASE(1), %ecx + xorl %edx, %edx + movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + wrmsr + post_code(0x25)
/* Enable MTRR. */ @@ -128,6 +139,30 @@ invd movl %eax, %cr0
+#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM) +update_microcode: + /* put the return address in %esp */ + movl $end_microcode_update, %esp + jmp update_bsp_microcode +end_microcode_update: +#endif + /* Disable caching to change MTRR's. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + /* Clear the mask valid to disable the MTRR */ + movl $MTRR_PHYS_MASK(1), %ecx + rdmsr + andl $(~MTRR_PHYS_MASK_VALID), %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + /* enable the 'no eviction' mode */ movl $NoEvictMod_MSR, %ecx rdmsr @@ -154,15 +189,9 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0
- /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRR_PHYS_BASE(1), %ecx - xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
post_code(0x28)
-
Kyösti Mälkki (Code Review) -
Patrick Georgi (Code Review)