Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/ee6c6f89_313d258b PS2, Line 15: Now, in this scenario, the SPI : flash linear address range is not registered as a resource (since the : common SPI driver in src/soc/intel/common/block/spi is shared across : multiple SPI controllers and therefore cannot distinguish where the : flash is actually located at)
I don't understand this. It's in common so that means it knows about the memory mapped flash for all platforms? That is what the code in block/fast_spi seems to do.
I don't think the fast_spi code has a PCI driver, the fast SPI PCI devices use the block/spi PCI driver (same driver for both fast SPI and GSPI, it exposes the SPI bus). For fast SPI, one would have to extend that driver. I would export `spi_bus_ops` and declare a new PCI driver.
There really should be something reserving that resource range as the allocator will otherwise use to to put PCI bars there.
+1
File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/62566/comment/db5202da_c32cb99d PS2, Line 165: mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, The only platform that does this is amd/pi/00730F01. I don't really know about AMD platforms, but I think this is because the BinaryPI blob sets up MTRRs.
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Angel Pons (Code Review)