[S] Change in coreboot[master]: soc/amd/common: Remove buildtime error for unknown cpu

[Martin L Roth (Code Review)]

Attention is currently required from: Martin Roth.

Hello Martin Roth,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/68245

to review the following change.

Change subject: soc/amd/common: Remove buildtime error for unknown cpu
......................................................................

soc/amd/common: Remove buildtime error for unknown cpu

This is not critical functionality and doesn't need a build-time error.
Having it as a build time error causes a chicken & egg issue where
the chipset needs to be added before it can be added to this file, but
the header file fails the build because the chipset is unknown.

It's not practical to exclude these files from the new platform builds
because the PSP functionality is thoroughly embedded into the coreboot
structure.

Signed-off-by: Martin Roth 
Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed
---
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
M src/soc/amd/common/block/psp/psp_efs.c
2 files changed, 26 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/68245/1

diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
index 1f93807..51b06a6 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h
@@ -19,11 +19,8 @@
 #elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO)
   #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f
   #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f
-#else
-  #error <Error: Unknown Processor>
 #endif

-
 struct second_gen_efs { /* todo: expand for Server products */
    uint32_t gen:1; /* Client products only use bit 0 */
    uint32_t reserved:31;
diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c
index feb0276..3aac9cb 100644
--- a/src/soc/amd/common/block/psp/psp_efs.c
+++ b/src/soc/amd/common/block/psp/psp_efs.c
@@ -2,6 +2,7 @@

#include <amdblocks/psp_efs.h>
 #include <arch/mmio.h>
+#include <assert.h>
 #include <boot_device.h>
 #include <commonlib/region.h>
 #include <types.h>
@@ -24,7 +25,13 @@
    if (!efs_is_valid())
    	return false;

+#ifndef SPI_MODE_FIELD
+	printk(BIOS_ERR,"Unknown cpu in psp_efs.h\n");
+	printk(BIOS_ERR,"SPI speed/mode not set.\n");
+	return false;
+#else
    *mode = efs->SPI_MODE_FIELD;
    *speed = efs->SPI_SPEED_FIELD;
    return true;
+#endif
 }