Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16002
-gerrit
commit 0ff809ec2f3ad18b66523811194c0b584bcc4899 Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Jul 31 14:15:49 2016 -0700
drivers/intel/fsp2_0: Disable display of FSP header
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image.
TEST=Build and run on Galileo Gen2
Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/drivers/intel/fsp2_0/Kconfig | 6 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/header_display.c | 58 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 13 +++++ src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 - src/drivers/intel/fsp2_0/util.c | 43 ---------------- 6 files changed, 79 insertions(+), 45 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4ff6116..1975293 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP.
+config DISPLAY_FSP_HEADER + bool "Display the FSP header + default n + help + Display the FSP header information when the FSP file is found. + config DISPLAY_HOBS bool "Display the hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 9982dcb..ccef72f 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c @@ -24,6 +25,7 @@ romstage-y += memory_init.c
ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c new file mode 100644 index 0000000..543c075 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Alexandru Gagniuc alexandrux.gagniuc@intel.com for Intel Corp.) + * (Written by Andrey Petrov andrey.petrov@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + + printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), + hdr->spec_version & 0xf); + printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", + revision.rev.major, + revision.rev.minor, + revision.rev.revision, + revision.rev.bld_num); + printk(BIOS_SPEW, "Type: %s/%s\n", + (hdr->component_attribute & 1 ) ? "release" : "debug", + (hdr->component_attribute & 2 ) ? "test" : "official"); + printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", + hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 26d13ae..1c05936 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -20,6 +20,19 @@ #include <soc/intel/common/util.h>
/*----------- + * HEADER + *----------- + */ +#if IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER) +void fsp_print_header_info(const struct fsp_header *hdr); +#else /* CONFIG_DISPLAY_FSP_HEADER */ +static inline __attribute__((always_inline)) void fsp_print_header_info( + const struct fsp_header *hdr) +{ +} +#endif /* CONFIG_DISPLAY_FSP_HEADER */ + +/*----------- * HOBs *----------- */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f5db37d..6351b32 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -42,8 +42,6 @@ struct fsp_header { };
enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -void fsp_print_header_info(const struct fsp_header *hdr); -void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
#if ENV_RAMSTAGE /* diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 108457d..7f064a5 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -59,49 +59,6 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) return CB_SUCCESS; }
-void fsp_print_header_info(const struct fsp_header *hdr) -{ - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; - - revision.val = hdr->fsp_revision; - - printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), - hdr->spec_version & 0xf); - printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n", - revision.rev.major, - revision.rev.minor, - revision.rev.revision, - revision.rev.bld_num); - printk(BIOS_DEBUG, "Type: %s/%s\n", - (hdr->component_attribute & 1 ) ? "release" : "debug", - (hdr->component_attribute & 2 ) ? "test" : "official"); - printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); - printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { - printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); - } - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { - printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); - printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); - } - -} - enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev) {
-
Lee Leahy