[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()

[SH Kim (Code Review)]

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email )

Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................

mb/google/{brya,hades}: use soc index for variant_update_power_limits()

The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the code
to get the proper pointer of the data for current CPU SKU.

BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.

Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim 
---
M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
2 files changed, 64 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81436/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
index 9c2d4aa..2235994 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
@@ -11,11 +11,40 @@

WEAK_DEV_PTR(dptf_policy);

+static struct soc_power_limits_config* get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	size_t i;
+	struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	uint16_t sa_pci_id;
+	u8 tdp;
+
+	if (!sa)
+		return NULL;
+
+	sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID);
+
+	tdp = get_cpu_tdp();
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
+				tdp == cpuid_to_adl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_adl[i].limits];
+		}
+	}
+
+	return NULL;
+}
+
 void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
 {
    if (!num_entries)
    	return;

+	struct soc_power_limits_config *soc_config = get_soc_power_limit_config();
+	if (!soc_config)
+		return;
+
    const struct device *policy_dev = DEV_PTR(dptf_policy);
    if (!policy_dev)
    	return;
@@ -29,20 +58,18 @@
    for (size_t i = 0; i < num_entries; i++) {
    	if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
    		struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
    		settings->pl1.min_power = limits[i].pl1_min_power;
    		settings->pl1.max_power = limits[i].pl1_max_power;
    		settings->pl2.min_power = limits[i].pl2_min_power;
    		settings->pl2.max_power = limits[i].pl2_max_power;
    		soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
-							   MILLIWATTS_TO_WATTS);
+				MILLIWATTS_TO_WATTS);
    		printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
-					limits[i].pl1_min_power,
-					limits[i].pl1_max_power,
-					limits[i].pl2_min_power,
-					limits[i].pl2_max_power,
-					limits[i].pl4_power);
+				limits[i].pl1_min_power,
+				limits[i].pl1_max_power,
+				limits[i].pl2_min_power,
+				limits[i].pl2_max_power,
+				limits[i].pl4_power);
    	}
    }
 }
diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
index 4858eb7..2235994 100644
--- a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
+++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
@@ -11,11 +11,40 @@

WEAK_DEV_PTR(dptf_policy);

+static struct soc_power_limits_config* get_soc_power_limit_config(void)
+{
+	config_t *config = config_of_soc();
+	size_t i;
+	struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT);
+	uint16_t sa_pci_id;
+	u8 tdp;
+
+	if (!sa)
+		return NULL;
+
+	sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID);
+
+	tdp = get_cpu_tdp();
+
+	for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
+		if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
+				tdp == cpuid_to_adl[i].cpu_tdp) {
+			return &config->power_limits_config[cpuid_to_adl[i].limits];
+		}
+	}
+
+	return NULL;
+}
+
 void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries)
 {
    if (!num_entries)
    	return;

+	struct soc_power_limits_config *soc_config = get_soc_power_limit_config();
+	if (!soc_config)
+		return;
+
    const struct device *policy_dev = DEV_PTR(dptf_policy);
    if (!policy_dev)
    	return;
@@ -29,8 +58,6 @@
    for (size_t i = 0; i < num_entries; i++) {
    	if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
    		struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
    		settings->pl1.min_power = limits[i].pl1_min_power;
    		settings->pl1.max_power = limits[i].pl1_max_power;
    		settings->pl2.min_power = limits[i].pl2_min_power;