[M] Change in coreboot[main]: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85603?usp=email )

Change subject: ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
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ec/google/chromeec: Publish LPC GMR address range via CREC _CRS

This change allows the Chrome EC (CREC) ACPI device to publish the LPC
Generic Memory Range (GMR) address range using the _CRS method.

The Google CREC driver can now parse this information to determine the
MMIO address map, enabling access to the LPC GMR register space.

This addresses the issue where the CREC driver was unable to
automatically determine the LPC GMR base address.

TEST=Able to build and boot google/brox.

without this patch:

brox-rev0 ~ # cat /proc/iomem | grep fe0

fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4

with this patch:

brox-rev0 ~ # cat /proc/iomem | grep fe0
fe000000-fe00ffff : INTC1026:00
fe000000-fe00ffff : intel_scu_ipc
fe03e000-fe03efff : 0000:00:1e.0
fe03e000-fe03e1ff : lpss_dev
fe03e000-fe03e1ff : serial
fe03e200-fe03e2ff : lpss_priv
fe03e800-fe03efff : idma64.4
fe03e800-fe03efff : idma64.4 idma64.4
fe0b0000-fe0bffff : GOOG0004:00

Change-Id: Ib3ea3e2a482f9eceaa8c15e38b7e708b156bc978
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85603
Reviewed-by: Kapil Porwal 
Reviewed-by: Caveh Jalali 
Tested-by: build bot (Jenkins) 
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/acpi/cros_ec.asl
2 files changed, 35 insertions(+), 15 deletions(-)

Approvals:
  Kapil Porwal: Looks good to me, approved
  build bot (Jenkins): Verified
  Caveh Jalali: Looks good to me, but someone else must approve

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index f0418ff..eae1fc6 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -167,6 +167,12 @@

If unsure, say N.

+config EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE
+	def_bool n
+	help
+	  Select this option to access LPC GMR (Generic Memory Range) Register to
+	  implement MMIO based communication between EC and AP firmware.
+
 endif # EC_GOOGLE_CHROMEEC

source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl
index 5b5229b..9cf1f66 100644
--- a/src/ec/google/chromeec/acpi/cros_ec.asl
+++ b/src/ec/google/chromeec/acpi/cros_ec.asl
@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)
+#define LPC_GMR_SIZE 0x10000
+#endif
+
 Device (CREC)
 {
    Name (_HID, "GOOG0004")
@@ -19,26 +23,36 @@
    #define EC_SYNC_SHARE_TYPE Exclusive
 #endif

-#ifdef EC_ENABLE_SYNC_IRQ
-	Name (_CRS, ResourceTemplate ()
+#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO)
+	Method (_CRS, 0x0, NotSerialized)
    {
-		Interrupt (ResourceConsumer, Level, ActiveLow,
-			   EC_SYNC_SHARE_TYPE)
+		Name (RBUF, ResourceTemplate()
    	{
-			EC_SYNC_IRQ
-		}
-	})
+#ifdef EC_ENABLE_SYNC_IRQ
+			Interrupt (ResourceConsumer, Level, ActiveLow, EC_SYNC_SHARE_TYPE) { EC_SYNC_IRQ }
 #endif

#ifdef EC_ENABLE_SYNC_IRQ_GPIO
-	Name (_CRS, ResourceTemplate ()
-	{
-		GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault,
-			 0x0000, "\_SB.GPIO", 0x00, ResourceConsumer, ,)
-		{
-			EC_SYNC_IRQ
-		}
-	})
+			GpioInt (Level, ActiveLow, EC_SYNC_SHARE_TYPE, PullDefault,
+				 0x0000, "\_SB.GPIO", 0x00, ResourceConsumer, ,)
+			{
+				EC_SYNC_IRQ
+			}
+#endif
+
+#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)
+		Memory32Fixed (ReadWrite, 0, 0, MADR)
+#endif
+		})
+
+#if CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)
+		CreateDWordField (RBUF, MADR._BAS, BAS0)
+		CreateDWordField (RBUF, MADR._LEN, LEN0)
+		BAS0 = _SB.PCI0.LPCB.GLGM()
+		LEN0 = LPC_GMR_SIZE
+#endif
+		Return (RBUF)
+	}
 #endif

#ifdef EC_ENABLE_MKBP_DEVICE