John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: Disable D3Code along with pass through mode ......................................................................
Disable D3Code along with pass through mode
The pass through mode(SW CM) RTD3 is not support until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware.
BUG=b:159050315 TEST=Verfiy S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42504/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926c..4bc8345 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@
# D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + register "TcssD3ColdEnable" = "0"
# DP port register "DdiPortAConfig" = "1" # eDP
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: Disable D3Code along with pass through mode ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@7 PS1, Line 7: Disable D3Code along with pass through mode Please add a prefix.
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: QS What is QS?
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: pass through mode(SW CM) Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: support supported
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@10 PS1, Line 10: upstream TBT firmware Please note the firmware versions.
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shamile Khan, Duncan Laurie, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42504
to look at the new patch set (#2).
Change subject: mb/google/volteer: Disable D3Code along with pass through mode ......................................................................
mb/google/volteer: Disable D3Code along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will needed to be reverted once PM RTD3 support is validated on QS platform.
BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42504/2
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Code along with pass through mode ......................................................................
Patch Set 2:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@7 PS1, Line 7: Disable D3Code along with pass through mode
Please add a prefix.
Done
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: support
supported
Done
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: QS
What is QS?
We are working on pre-QS silicon. QS will be next revision. Sorry, the term "QS" is what we are supposed to use. I add further comments about this temporary patch to be reverted once the PM RTD3 is validated on QS platform.
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@9 PS1, Line 9: pass through mode(SW CM)
Please add a space before the (.
Done
https://review.coreboot.org/c/coreboot/+/42504/1//COMMIT_MSG@10 PS1, Line 10: upstream TBT firmware
Please note the firmware versions.
The upstream TBT firmware is engineering version as named "signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.bin".
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shamile Khan, Duncan Laurie, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42504
to look at the new patch set (#3).
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
mb/google/volteer: Disable D3Cold along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will needed to be reverted once PM RTD3 support is validated on QS platform.
BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42504/3
Divya Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
Patch Set 4: Code-Review+1
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
Patch Set 4: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@7 PS4, Line 7: Disable D3Cold Disable D3cold for TCSS otherwise D3cold for what device?
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@7 PS4, Line 7: Disable D3Cold
Disable D3cold for TCSS […]
XHCI can only have D3Hot support. This temporary change limits TBT PCIe root ports and DMA with D3Hot only as well, not allowing their entry to lower D3Cold due to upstream SW CM TBT firmware restriction.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold along with pass through mode ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@7 PS4, Line 7: Disable D3Cold
XHCI can only have D3Hot support. […]
Sorry, I meant can you change the wording to say "D3cold for TCSS" or something like that.
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@12 PS4, Line 12: needed need
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shamile Khan, Duncan Laurie, Divya Sasidharan, Tim Wawrzynczak, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42504
to look at the new patch set (#5).
Change subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode ......................................................................
mb/google/volteer: Disable D3Cold for TCSS along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform.
BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42504/5
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@7 PS4, Line 7: Disable D3Cold
Sorry, I meant can you change the wording to say "D3cold for TCSS" or something like that.
done
https://review.coreboot.org/c/coreboot/+/42504/4//COMMIT_MSG@12 PS4, Line 12: needed
need
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode ......................................................................
Patch Set 5: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42504 )
Change subject: mb/google/volteer: Disable D3Cold for TCSS along with pass through mode ......................................................................
mb/google/volteer: Disable D3Cold for TCSS along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform. D3Cold is needed to be disabled along with upstream TBT firmware signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix. This temporary patch will need to be reverted once PM RTD3 support is validated on QS platform.
BUG=b:159050315 TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Divya Sasidharan divya.s.sasidharan@intel.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified John Zhao: Looks good to me, but someone else must approve Divya Sasidharan: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f2e427f..9732aa8 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@
# D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + register "TcssD3ColdEnable" = "0"
# DP port register "DdiPortAConfig" = "1" # eDP