Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/common: Add Device id for Tigerlake Dual Core ......................................................................
soc/common: Add Device id for Tigerlake Dual Core
Add device id for Tigerlake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2..7434cf1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3444,6 +3444,7 @@ #define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8..59076fc 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -397,6 +397,7 @@ PCI_DEVICE_ID_INTEL_CML_H_4_2, PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, + PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, PCI_DEVICE_ID_INTEL_TGL_ID_Y, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..f38e9cf 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -46,6 +46,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/common: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 1: Code-Review+1
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/common: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38774/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38774/1//COMMIT_MSG@7 PS1, Line 7: soc/common soc/intel/tigerlake
https://review.coreboot.org/c/coreboot/+/38774/1/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38774/1/src/include/device/pci_ids.... PS1, Line 3447: #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 do we want to keep these sorted by name?
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/common: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38774/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38774/1//COMMIT_MSG@7 PS1, Line 7: soc/common
soc/intel/tigerlake
Ack
https://review.coreboot.org/c/coreboot/+/38774/1/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38774/1/src/include/device/pci_ids.... PS1, Line 3447: #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04
do we want to keep these sorted by name?
Ack
Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, caveh jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38774
to look at the new patch set (#2).
Change subject: soc/common: Add Device id for Tigerlake Dual Core ......................................................................
soc/common: Add Device id for Tigerlake Dual Core
Add device id for Tigerlake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/2
Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, caveh jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38774
to look at the new patch set (#3).
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
soc/tigerlake: Add Device id for Tigerlake Dual Core
Add device id for Tigerlake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/3
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 3: Code-Review+1
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 3: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 4: Code-Review+1
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG@7 PS4, Line 7: Tigerlake Tiger Lake
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG@16 PS4, Line 16: Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd In a lot of commits this is directly above the BUG line.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG@7 PS4, Line 7: Tigerlake
Tiger Lake
Ack
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tigerlake Dual Core ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38774/4//COMMIT_MSG@16 PS4, Line 16: Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd
In a lot of commits this is directly above the BUG line.
Ack
Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, caveh jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38774
to look at the new patch set (#5).
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
soc/tigerlake: Add Device id for Tiger Lake Dual Core
Add device id for Tiger Lake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/5
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38774/6/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38774/6/src/include/device/pci_ids.... PS6, Line 3446: #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 : #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 : #define PCI_DEVICE_ID_INTEL_TGL_ID_U now that i'm looking at this a 2nd time, i think it makes more sense to order these alphabetically like i originally commented rather than numerically.
this means we can have these ordered identically in systemagent.c as well.
https://review.coreboot.org/c/coreboot/+/38774/6/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38774/6/src/soc/intel/common/block/... PS6, Line 399: PCI_DEVICE_ID_INTEL_TGL_ID_U, : PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, : PCI_DEVICE_ID_INTEL_TGL_ID_U_1, please match order in pci_ids.h (alphabetical) unless there's a functional reason for a different ordering.
Hello Raj Astekar, Patrick Rudolph, Nick Vaccaro, Wonkyu Kim, caveh jalali, build bot (Jenkins), Shaunak Saha, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38774
to look at the new patch set (#7).
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
soc/tigerlake: Add Device id for Tiger Lake Dual Core
Add device id for Tiger Lake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38774/7
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 7: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 7: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38774/6/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/38774/6/src/include/device/pci_ids.... PS6, Line 3446: #define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 : #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 : #define PCI_DEVICE_ID_INTEL_TGL_ID_U
now that i'm looking at this a 2nd time, i think it makes […]
Done
https://review.coreboot.org/c/coreboot/+/38774/6/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/38774/6/src/soc/intel/common/block/... PS6, Line 399: PCI_DEVICE_ID_INTEL_TGL_ID_U, : PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, : PCI_DEVICE_ID_INTEL_TGL_ID_U_1,
please match order in pci_ids.h (alphabetical) […]
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 7: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
Patch Set 7: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38774 )
Change subject: soc/tigerlake: Add Device id for Tiger Lake Dual Core ......................................................................
soc/tigerlake: Add Device id for Tiger Lake Dual Core
Add device id for Tiger Lake Dual core part.
BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot
Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/tigerlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e117ac2..c6602c4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3445,6 +3445,7 @@ #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 #define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 #define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04 #define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10 #define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a #define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 4c7d8c8..e660dbf 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -398,6 +398,7 @@ PCI_DEVICE_ID_INTEL_CML_H_8_2, PCI_DEVICE_ID_INTEL_TGL_ID_U, PCI_DEVICE_ID_INTEL_TGL_ID_U_1, + PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, PCI_DEVICE_ID_INTEL_TGL_ID_Y, PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, PCI_DEVICE_ID_INTEL_JSL_EHL, diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index 127994d..f38e9cf 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -46,6 +46,7 @@ } mch_table[] = { { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, + { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, { PCI_DEVICE_ID_INTEL_JSL_PRE_PROD, "Jasperlake Pre Prod" }, { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" },