Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46135 )
Change subject: sb/intel/lynxpoint: fix typo ......................................................................
sb/intel/lynxpoint: fix typo
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46135/1
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 66e46d3..e0d09fd 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@
pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
- /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25);
pci_and_config8(dev, 0xf5, 0x3f);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46135 )
Change subject: sb/intel/lynxpoint: fix typo ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46135 )
Change subject: sb/intel/lynxpoint: fix typo ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46135/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46135/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/lynxpoint: fix typo … in comment
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46135
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint/pcie.c: fix typo in comment ......................................................................
sb/intel/lynxpoint/pcie.c: fix typo in comment
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46135/2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46135 )
Change subject: sb/intel/lynxpoint/pcie.c: fix typo in comment ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46135/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46135/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/lynxpoint: fix typo
… in comment
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46135 )
Change subject: sb/intel/lynxpoint/pcie.c: fix typo in comment ......................................................................
sb/intel/lynxpoint/pcie.c: fix typo in comment
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46135 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 2da14ed..0ede943 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -659,7 +659,7 @@
pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74);
- /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25);
pci_and_config8(dev, 0xf5, 0x3f);
-
Angel Pons (Code Review) -
Matt DeVillier (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)