Change in coreboot[master]: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61536 )

Change subject: soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
......................................................................

soc/intel/alderlake: Enable USB2 port reset message on Type-C ports

This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.

The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state

BUG=b:193287279
TEST=Built coreboot on Gimble and tested type A pen drive detects as
super speed device

Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea
Signed-off-by: Anil Kumar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536
Tested-by: build bot (Jenkins) 
Reviewed-by: Sridhar Siricilla 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/include/soc/usb.h
2 files changed, 5 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Sridhar Siricilla: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 8284980..8aa20a8 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -439,6 +439,9 @@
    		s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
    	else
    		s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
+
+		if (config->usb2_ports[i].type_c)
+			s_cfg->PortResetMessageEnable[i] = 1;
    }

for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index e339c72..70a367e 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -31,6 +31,7 @@
    uint8_t tx_emp_enable;
    uint8_t pre_emp_bias;
    uint8_t pre_emp_bit;
+	uint8_t type_c;
 };

/* USB Overcurrent pins definition */
@@ -112,6 +113,7 @@
    .tx_emp_enable = USB2_PRE_EMP_ON, \
    .pre_emp_bias  = USB2_BIAS_56P3MV, \
    .pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+	.type_c	       = 1, \
 }

struct usb3_port_config {

9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.