EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: correct USB3 OC pin error ......................................................................
mb/google/drallion: correct USB3 OC pin error
USB3 OC pin was configured wrong pin. Follow HW circuit to set it.
BUG=b:147869924 TEST=USB function works well
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38885/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5d..92f3fb9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY"
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: correct USB3 OC pin error ......................................................................
Patch Set 1:
Please help review this. IIUC USB3 OC is doesn't matter though..
Hello Mathew King, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38885
to look at the new patch set (#2).
Change subject: mb/google/drallion: correct USB3 OC pin configuration ......................................................................
mb/google/drallion: correct USB3 OC pin configuration
USB3 OC pin was configured wrong pin. Follow HW circuit to set it.
BUG=b:147869924 TEST=USB function works well and OC function is correspond to the right port.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38885/2
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: correct USB3 OC pin configuration ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: correct USB3 OC pin configuration ......................................................................
Patch Set 2: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@7 PS2, Line 7: correct Correct
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@9 PS2, Line 9: USB3 OC pin was configured wrong pin. Follow HW circuit to set it. USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly.
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@12 PS2, Line 12: is correspond corresponds
Hello Mathew King, Paul Menzel, Duncan Laurie, John Su, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38885
to look at the new patch set (#3).
Change subject: mb/google/drallion: Correct USB3 OC pin configuration ......................................................................
mb/google/drallion: Correct USB3 OC pin configuration
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly.
BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38885/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: Correct USB3 OC pin configuration ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@7 PS2, Line 7: correct
Correct
Done
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@9 PS2, Line 9: USB3 OC pin was configured wrong pin. Follow HW circuit to set it.
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly.
Done
https://review.coreboot.org/c/coreboot/+/38885/2//COMMIT_MSG@12 PS2, Line 12: is correspond
corresponds
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: Correct USB3 OC pin configuration ......................................................................
mb/google/drallion: Correct USB3 OC pin configuration
USB3 OC pin is configured for the wrong pin. Follow HW circuit (schematics) to set it correctly.
BUG=b:147869924 TEST=USB function works well and OC function is corresponds to the right port.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885 Reviewed-by: John Su john_su@compal.corp-partner.google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve John Su: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5d..92f3fb9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY"
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EricR Lai (Code Review) -
John Su (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)