Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17695
-gerrit
commit e50365173f13ee1f1bf493dce23adb7d0fd52b5f Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Dec 2 08:56:05 2016 +0200
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/device/device_util.c | 44 ++++++++++++++++++++ src/include/device/device.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 21 +++++----- src/northbridge/amd/agesa/family12/northbridge.c | 13 +++--- src/northbridge/amd/agesa/family14/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15rl/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 +-- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 +-- src/northbridge/amd/amdfam10/northbridge.c | 9 +---- src/northbridge/amd/pi/00630F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00660F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00670F00/northbridge.c | 11 +---- src/northbridge/amd/pi/00730F01/northbridge.c | 11 +---- src/northbridge/intel/fsp_rangeley/Kconfig | 4 ++ src/northbridge/intel/fsp_rangeley/northbridge.c | 27 ++++++------- src/northbridge/intel/fsp_sandybridge/Kconfig | 4 ++ .../intel/fsp_sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/intel/i3100/northbridge.c | 10 +---- src/northbridge/intel/i945/northbridge.c | 45 +++++---------------- src/northbridge/intel/nehalem/Kconfig | 4 ++ src/northbridge/intel/nehalem/northbridge.c | 11 +---- src/northbridge/intel/sandybridge/Kconfig | 4 ++ src/northbridge/intel/sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/northbridge.c | 5 +-- src/soc/intel/fsp_baytrail/northcluster.c | 28 ++++++------- src/soc/intel/sch/Kconfig | 4 ++ src/soc/intel/sch/northbridge.c | 43 +++++--------------- 29 files changed, 177 insertions(+), 276 deletions(-)
diff --git a/src/device/device_util.c b/src/device/device_util.c index 56afefd..22de249 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -23,6 +23,7 @@ #include <device/path.h> #include <device/pci_def.h> #include <device/resource.h> +#include <lib.h> #include <string.h>
/** @@ -888,6 +889,49 @@ void fixed_mem_resource(device_t dev, unsigned long index, resource->flags |= type; }
+#if IS_ENABLED(CONFIG_PCI) +int mmconf_resource_init(struct resource *resource, bool bar64, + uintptr_t base, int buses) +{ + resource->base = base; + resource->size = buses * MiB; + resource->align = log2(resource->size); + resource->gran = log2(resource->size); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* 64-bit BAR or MSR. */ + if (bar64 && IS_ENABLED(CONFIG_ARCH_RAMSTAGE_X86_64)) + resource->limit = (1ULL << cpu_phys_address_size()) - 1; + else + resource->limit = (1ULL << 32) - 1; + + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + return 0; +} + +void mmconf_resource32(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + if (!resource) + return; + + mmconf_resource_init(resource, 0, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} + +void mmconf_resource64(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + if (!resource) + return; + + mmconf_resource_init(resource, 1, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} +#endif + void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..36edb79 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,11 @@ void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type);
+int mmconf_resource_init(struct resource *res, bool bar64, uintptr_t base, + int buses); +void mmconf_resource32(struct device *dev, unsigned long index); +void mmconf_resource64(struct device *dev, unsigned long index); + void scan_smbus(device_t bus); void scan_static_bus(device_t bus); void scan_lpc_bus(device_t bus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2a54892..7408e50 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -424,6 +424,13 @@ static void amdfam10_read_resources(device_t dev) amdfam10_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); }
static void amdfam10_set_resource(device_t dev, struct resource *resource, @@ -530,6 +537,11 @@ static void amdfam10_set_resources(device_t dev) assign_resources(bus); } } + + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } }
static void mcf0_control_init(struct device *dev) @@ -1096,19 +1108,10 @@ static void cpu_bus_init(device_t dev)
static void cpu_bus_read_resources(device_t dev) { - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); }
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 6f2896a..5ef7a90 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -300,6 +300,14 @@ static void read_resources(device_t dev) amdfam12_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }
@@ -649,11 +657,6 @@ static void cpu_bus_read_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
- struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f92183e..08d1c49 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -302,11 +302,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5fc9833..c5e2921 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -326,11 +326,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index b5f7690..2417933 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -326,11 +326,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2353126..7862e60 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -325,11 +325,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 63e1c2e..23057a9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -325,11 +325,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the APIC_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index cc2e6f9..b384ca9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -741,14 +741,7 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev);
/* We have MMCONF_SUPPORT, create the resource window. */ - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058);
/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 4872db0..1695808 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -309,15 +309,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -335,7 +326,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 4c1254c..9f6ae1f 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 9a39410..521a32c 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 44f91e2..d97d875 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -312,15 +312,6 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -338,7 +329,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); }
static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index bc735264..fdb5566 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -24,6 +24,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000
+config MMCONF_BUS_NUMBER + int + default 256 + choice prompt "Set TSEG Size" default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index f01333e..34426c7 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -57,13 +57,12 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg;
*base = 0; - *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) @@ -76,25 +75,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; /* 256MB ECAM range */ - return 1; + return 256;
}
static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - }
resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; @@ -154,9 +141,19 @@ static void mc_add_dram_resources(device_t dev)
static void mc_read_resources(device_t dev) { + u32 pcie_config_base; + int buses; + /* Call the normal read_resources */ pci_dev_read_resources(dev);
+ /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + } + /* Calculate and add DRAM resources. */ mc_add_dram_resources(dev); } diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 89326b4..cfcfc34 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -30,6 +30,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/fsp_sandybridge/bootblock.c"
+config MMCONF_BUS_NUMBER + int + default 64 + config VGA_BIOS_ID string default "8086,0106" diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 50615b5..877d85f 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -62,18 +62,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg;
*base = 0; - *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0;
+ /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0))) @@ -82,16 +82,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; }
return 0; @@ -99,21 +96,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); }
@@ -256,24 +240,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses;
pci_dev_read_resources(dev);
- /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } }
static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 8025ac3..65107de 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -32,9 +32,6 @@ #include <arch/acpi.h>
-static u32 max_bus; - - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -139,14 +136,9 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - struct resource *resource; - pci_dev_read_resources(dev);
- resource = new_resource(dev, 0xcf); - resource->base = 0xe0000000; - resource->size = max_bus * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource32(dev, 0xcf); }
static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 5d18591..c98a39f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -27,13 +27,12 @@ #include <arch/acpi.h> #include "i945.h"
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg;
*base = 0; - *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) @@ -47,36 +46,18 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; }
return 0; }
-static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } -} - static void pci_domain_set_resources(device_t dev) { uint32_t pci_tolm; @@ -153,8 +134,6 @@ static void pci_domain_set_resources(device_t dev) uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10);
- add_fixed_resources(dev, 7); - assign_resources(dev->link_list); }
@@ -173,19 +152,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses;
pci_dev_read_resources(dev);
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } }
static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 4dada50..884660a 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
if NORTHBRIDGE_INTEL_NEHALEM
+config MMCONF_BUS_NUMBER + int + default 256 + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 06c0a96..cc782e9 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -69,11 +69,6 @@ static void add_fixed_resources(struct device *dev, int index) 0xfed1c000-0xfed20000 RCBA 0xfed90000-0xfed94000 IOMMU 0xff800000-0xffffffff ROM. */ - resource = new_resource(dev, index++); - resource->base = (resource_t) 0xe0000000; - resource->size = (resource_t) 0x10000000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++); resource->base = (resource_t) 0xfed00000; @@ -98,10 +93,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
- /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, @@ -119,6 +110,8 @@ static void mc_read_resources(device_t dev)
pci_dev_read_resources(dev);
+ mmconf_resource64(dev, 0x50); + tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_TOUUD); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index c78b397..15f2aab 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -71,6 +71,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c"
+config MMCONF_BUS_NUMBER + int + default 64 + if USE_NATIVE_RAMINIT
config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index fe1a07c..0c30b2d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -61,18 +61,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384;
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg;
*base = 0; - *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0;
+ /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0))) @@ -81,16 +81,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; }
return 0; @@ -98,21 +95,8 @@ static int get_pcie_bar(u32 *base, u32 *len)
static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
- if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); reserved_ram_resource(dev, index++, 0xc0000 >> 10, @@ -276,24 +260,17 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses;
pci_dev_read_resources(dev);
- /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + } }
static void mc_set_resources(device_t dev) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 73d40ad..4b1e6cc 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -33,6 +33,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000
+config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "1106,7122" diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index a4a8ece..ffeaada0 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -297,10 +297,7 @@ static void vx900_read_resources(device_t dev) /* Now do the same for our MMCONF * We always run with MMCONF enabled. We need to access the extended * config space when configuring PCI-Express links */ - res = new_resource(dev, idx++); - res->size = 256 * MiB; - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + mmconf_resource32(dev, idx++);
pci_domain_read_resources(dev); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index bf1a388..d6f12dc 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -86,18 +86,18 @@ uint32_t nc_read_top_of_low_memory(void) return fsp_mem_base; }
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg;
*base = 0; - *len = 0;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0;
+ /* FIXME: This is 64bit BAR. */ pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG);
if (!(pciexbar_reg & (1 << 0))) @@ -105,26 +105,13 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; /* 256MB ECAM range */ - return 1; + return 256;
}
static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - }
resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; @@ -182,9 +169,18 @@ static void mc_add_dram_resources(device_t dev)
static void nc_read_resources(device_t dev) { + u32 pcie_config_base; + int buses; + /* Call the normal read_resources */ pci_dev_read_resources(dev);
+ /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + }
/* Calculate and add DRAM resources. */ mc_add_dram_resources(dev); diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index 2456df7..abdee44 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -28,6 +28,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "soc/intel/sch/bootblock.c"
+config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "8086,8108" diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 390a0bc..07b17c0 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -27,7 +27,7 @@ #include <arch/acpi.h> #include "sch.h"
-static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; @@ -50,18 +50,15 @@ static int get_pcie_bar(u32 *base, u32 *len) case 0: /* 256MB */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: /* 128M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: /* 64M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; }
return 0; @@ -70,16 +67,6 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - }
printk(BIOS_DEBUG, "Adding CMC shadow area\n"); resource = new_resource(dev, index++); @@ -198,28 +185,20 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses;
pci_dev_read_resources(dev);
/* - * So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - - /* * We use 0xcf as an unused index for our PCIe bar so that we find * it again. */ - resource = new_resource(dev, 0xcf); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size); - printk(BIOS_DEBUG, - "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), - (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } }
static void mc_set_resources(device_t dev)
-
Kyösti Mälkki