Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45814 )
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/1
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d..59c61c4 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c \ No newline at end of file diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000..5d8d482 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +}
Hello Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45814
to look at the new patch set (#2).
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45814
to look at the new patch set (#4).
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/4
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45814
to look at the new patch set (#5).
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45814 )
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
Patch Set 5: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45814 )
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45814 )
Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ......................................................................
mb/emulation/q35: Define pm_acpi_smi_cmd_port
The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port.
This will be used by the common save state handler.
Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d..ddcf6da 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000..5d8d482 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +}
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)