Change in coreboot[master]: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification opt...

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Aamir Bohra, Naresh Solanki, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45723

to look at the new patch set (#3).

Change subject: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification optional
......................................................................

soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification optional

Low Power Audio and Intel Smart Sound Technology, which includes
features like Wake-on-Voice, require the XTAL to run even in S0ix.
This requires the XTAL S0ix qualification bit to make the PMC ignore the
XTAL state, which normally blocks S0ix.

However, not all devices support or use the aforementioned audio
technologies and keeping XTAL running draws about 2 mW of (battery)
power for no reason in low power states.

This patch adds a new devicetree option for XTAL S0ix (dis)qualification
to make this setting conditional.

This change also adds the newly introduced devicetree option to allow
S0ix being entered with XTAL running.

Signed-off-by: Michael Niewöhner 
Change-Id: I17bac9b06e5291b1548704744e872b22b2435c9c
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/finalize.c
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/finalize.c
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/finalize.c
24 files changed, 63 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45723/3