Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: addtional pin mux for Camera ......................................................................
mb/intel/tglrvp: addtional pin mux for Camera
Add addtional pin mux for I2C3, I2C5 for Camera. These pin mux were done in FSPs, this pin mux is for bypassing pin mux in FSPs.
BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from OS console
media-ctl -V ""Intel IPU6 CSI-2 5":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI-2 5":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""ov8856 18-0010":0 -> "Intel IPU6 CSI-2 5":0[1]" media-ctl -V ""Intel IPU6 CSI2 BE":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [crop:(0,0)/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""Intel IPU6 CSI-2 5":1 -> "Intel IPU6 CSI2 BE":0[1]" media-ctl -l ""Intel IPU6 CSI2 BE":1 -> "Intel IPU6 CSI2 BE capture":0[1]" yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39201/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 8638b80..9dab272 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -24,6 +24,10 @@ PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_R6, 0, PLTRST),
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39201
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: pin mux for Camera ......................................................................
mb/intel/tglrvp: pin mux for Camera
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from OS console
media-ctl -V ""Intel IPU6 CSI-2 5":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI-2 5":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""ov8856 18-0010":0 -> "Intel IPU6 CSI-2 5":0[1]" media-ctl -V ""Intel IPU6 CSI2 BE":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [crop:(0,0)/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""Intel IPU6 CSI-2 5":1 -> "Intel IPU6 CSI2 BE":0[1]" media-ctl -l ""Intel IPU6 CSI2 BE":1 -> "Intel IPU6 CSI2 BE capture":0[1]" yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39201/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: pin mux for Camera ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39201/2//COMMIT_MSG@7 PS2, Line 7: mb/intel/tglrvp: pin mux for Camera Please make the commit message summary a statement by adding a verb (in imperative mood):
Add pin mux for camera
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39201
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
mb/intel/tglrvp: Add pin mux for Camera
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from OS console
media-ctl -V ""Intel IPU6 CSI-2 5":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI-2 5":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""ov8856 18-0010":0 -> "Intel IPU6 CSI-2 5":0[1]" media-ctl -V ""Intel IPU6 CSI2 BE":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [crop:(0,0)/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""Intel IPU6 CSI-2 5":1 -> "Intel IPU6 CSI2 BE":0[1]" media-ctl -l ""Intel IPU6 CSI2 BE":1 -> "Intel IPU6 CSI2 BE capture":0[1]" yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/39201/3
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39201/2//COMMIT_MSG@7 PS2, Line 7: mb/intel/tglrvp: pin mux for Camera
Please make the commit message summary a statement by adding a verb (in imperative mood): […]
Ack
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3: Code-Review+1
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... PS3, Line 27: PLTRST does reset need to happen on DEEP or is PLTRST sufficient?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... PS3, Line 27: PLTRST
does reset need to happen on DEEP or is PLTRST sufficient?
Silicon reference code use TGLRST and we're following silicon reference code.
caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... PS3, Line 27: PLTRST
Silicon reference code use TGLRST and we're following silicon reference code.
ok, does that mean we should change volteer to use PLTRST? it currently uses DEEP.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c:
https://review.coreboot.org/c/coreboot/+/39201/3/src/mainboard/intel/tglrvp/... PS3, Line 27: PLTRST
ok, does that mean we should change volteer to use PLTRST? […]
We're checking PCH team for using DEEP. We'll provide information soon.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39201 )
Change subject: mb/intel/tglrvp: Add pin mux for Camera ......................................................................
mb/intel/tglrvp: Add pin mux for Camera
Add additional pin mux for I2C3, I2C5 for Camera. These pin muxes were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none BRANCH=none TEST=Build with pin mux bypass FSP and boot tigerlake rvp board and check camera
Simple test method to check camera: capture image by below commands from OS console
media-ctl -V ""Intel IPU6 CSI-2 5":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI-2 5":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""ov8856 18-0010":0 -> "Intel IPU6 CSI-2 5":0[1]" media-ctl -V ""Intel IPU6 CSI2 BE":0 [fmt:SGRBG10/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [crop:(0,0)/3280x2464]" media-ctl -V ""Intel IPU6 CSI2 BE":1 [fmt:SGRBG10/3280x2464]" media-ctl -l ""Intel IPU6 CSI-2 5":1 -> "Intel IPU6 CSI2 BE":0[1]" media-ctl -l ""Intel IPU6 CSI2 BE":1 -> "Intel IPU6 CSI2 BE capture":0[1]" yavta -u -c5 -n5 -I -s 3280x2464 --file=/tmp/frame-#.bin -f SGRBG10
$(media-ctl -e "Intel IPU6 CSI2 BE capture")
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9ad0e5ed452d2b2e8c674abe2a647a0a9c59188e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39201 Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Srinidhi N Kaushik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 073926a..30d148a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -24,6 +24,10 @@ PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */ + PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_B9, NONE, PLTRST, NF1), /* I2C5_SDA */ + PAD_CFG_NF(GPP_B10, NONE, PLTRST, NF1), /* I2C5_SCL */ PAD_CFG_GPO(GPP_B23, 0, PLTRST), PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_R6, 0, PLTRST),