Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71609 )
Change subject: WIP: mb/hp/t620: Add new board HP T620 ......................................................................
WIP: mb/hp/t620: Add new board HP T620
This is the diff applied to the previous commit to change the biostar/a68n_5200 port into support for new board: HP T620 thin client. This work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. It has a socketed SOIC8 chip and SIO accessible serial, making it a good target for testing/maintaining this platform.
coreboot console works over serial COMA by default. Board is fanless, so no need for fan control.
TESTED: Boots SeaBIOS 1.14.0 and to debian 11, NIC works, serial works.
Have had 120 days of uptime with this particular port and no issues.
Missing: - Audio verb table (deleted) - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board)
Caveat: Without VGA BIOS rom there are no displays. VGA ROM was extracted from /dev/mem @ 0xC0000 on a running system and one DP was tested to work.
NB: Since bringing back AGESA code with resource allocator v4 and parallel mp init, this board no longer boots due to some kind of CBFS alignment issue, I need some help to figure this out.
cbfs:
This image contains the following sections that can be manipulated with this tool:
'RW_MRC_CACHE' (size 65536, offset 0) 'COREBOOT' (CBFS, size 8322560, offset 66048)
It is possible to perform either the write action or the CBFS add/remove actions on every section listed above. To see the image's read-only sections as well, rerun with the -w option. CBFSPRINT coreboot.rom
FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs_master_header 0x0 cbfs header 32 none config 0x80 raw 2327 LZMA (6878 decompressed) revision 0xa00 raw 717 none build_info 0xd00 raw 89 none fallback/dsdt.aml 0xd80 raw 5950 none cmos_layout.bin 0x2500 cmos_layout 616 none fallback/postcar 0x27c0 stage 21688 none payload_config 0x7cc0 raw 1621 none payload_revision 0x8340 raw 235 none (empty) 0x8480 null 31012 none apu/amdfw 0xfdc0 raw 69632 none fallback/romstage 0x20e00 stage 386080 none fallback/ramstage 0x7f2c0 stage 125180 LZMA (283964 decompressed) pci1002,9837.rom 0x9dc40 optionrom 65536 none fallback/payload 0xadc80 simple elf 72756 none (empty) 0xbf900 null 7524836 none bootblock 0x7ecb00 bootblock 12992 none ... Built hp/t620 (T620)
tail of coreboot log: ... [INFO ] CBFS: Found 'pci1002,9837.rom' @0x9dc40 size 0x10000 in mcache @0x5ffdd2a4 [NOTE ] Mapping PCI device 10029837 to 10029830 [DEBUG] In CBFS, ROM address for PCI: 00:01.0 = 0xff8ade6c [DEBUG] Copying VBIOS image from 0xff8ade6c [DEBUG] ACPI: * VFCT at 5fe9d420 [DEBUG] ACPI: added table 8/32, length now 68 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 9/32, length now 72 [INFO ] ACPI: done. [DEBUG] ACPI tables: 89808 bytes. [DEBUG] smbios_write_tables: 5fe8e000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-1385-g5be491174b' [DEBUG] SMBIOS tables: 529 bytes. [DEBUG] Writing table forward entry at 0x00000500 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 80 [EMERG] ASSERTION ERROR: file 'src/lib/coreboot_table.c', line 428
Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Signed-off-by: Damien Zammit damien@zamaudio.com --- M src/mainboard/hp/t620/BiosCallOuts.c M src/mainboard/hp/t620/Kconfig M src/mainboard/hp/t620/Kconfig.name M src/mainboard/hp/t620/board_info.txt M src/mainboard/hp/t620/bootblock.c M src/mainboard/hp/t620/devicetree.cb 6 files changed, 128 insertions(+), 210 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/71609/1
diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c index f1560c4..a0ac3f0 100644 --- a/src/mainboard/hp/t620/BiosCallOuts.c +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -5,8 +5,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h>
-#include "imc.h" - const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, @@ -24,20 +22,6 @@ * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} };
@@ -47,113 +31,6 @@ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} };
-#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; @@ -164,7 +41,4 @@ { /* Azalia Controller OEM Codec Table Pointer */ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); } diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig index 256121c..f897bab 100644 --- a/src/mainboard/hp/t620/Kconfig +++ b/src/mainboard/hp/t620/Kconfig @@ -1,24 +1,22 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_BIOSTAR_A68N5200_CLONE +if BOARD_HP_T620
config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_ITE_IT8728F + select SUPERIO_ASPEED_AST2400 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_8192 select GFXUMA
config MAINBOARD_DIR default "hp/t620"
config MAINBOARD_PART_NUMBER - default "A68N5200" + default "T620"
config HW_MEM_HOLE_SIZEK hex @@ -40,4 +38,4 @@ bool default n
-endif +endif # BOARD_HP_T620 diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name index e893341..fd55b76 100644 --- a/src/mainboard/hp/t620/Kconfig.name +++ b/src/mainboard/hp/t620/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200_CLONE - bool "A68N-5200-CLONE" +config BOARD_HP_T620 + bool "T620" diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt index b351b8e..4132ada 100644 --- a/src/mainboard/hp/t620/board_info.txt +++ b/src/mainboard/hp/t620/board_info.txt @@ -1 +1,2 @@ Category: eval +Socketed Flash: Y diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c index 70bc10c..5226f4a 100644 --- a/src/mainboard/hp/t620/bootblock.c +++ b/src/mainboard/hp/t620/bootblock.c @@ -4,27 +4,10 @@ #include <bootblock_common.h> #include <stdint.h> #include <device/pci_ops.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h>
-#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - u32 reg32; - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - reg32 = misc_read32(0x28); - reg32 &= 0xfff8ffff; - misc_write32(0x28, reg32); - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = misc_read32(0x40); - reg32 &= 0xffffbffb; - misc_write32(0x40, reg32); -} +#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART2)
void bootblock_mainboard_early_init(void) { @@ -35,7 +18,7 @@
/* Set LPC decode enables. */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pci_write_config32(dev, 0x44, 0xff03ffc0);
/* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); @@ -47,11 +30,6 @@ byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte);
- /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Enable serial output on it8728f */ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* Enable serial output */ + aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb index c036b65..ed6fa58 100644 --- a/src/mainboard/hp/t620/devicetree.cb +++ b/src/mainboard/hp/t620/devicetree.cb @@ -8,15 +8,15 @@ end
device domain 0 on - subsystemid 0x1022 0x1410 inherit + subsystemid 0x103c 0x2187 inherit chip northbridge/amd/agesa/family16kb device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal HDMI Audio device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC + device pci 2.1 off end + device pci 2.2 on end + device pci 2.3 on end device pci 2.4 off end # Edge Connector device pci 2.5 off end # Edge Connector end #chip northbridge/amd/agesa/family16kb @@ -28,42 +28,23 @@ device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pci 14.0 on end # SMBus + device pci 14.2 on end # Audio Azalia + device pci 14.3 on # LPC + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "0" + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 on # SUART2 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0x71 = 3 + irq 0xf0 = 2 + end + end end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F + end end #LPC device pci 14.7 off end # SD end #chip southbridge/amd/agesa/hudson @@ -75,12 +56,10 @@ device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + register "spdAddrLookup" = "{ + { {0xA0, 0xA2}, {0x00, 0x00}, }, + { {0x00, 0x00}, {0x00, 0x00}, }, }" end - - end #domain + end end #northbridge/amd/agesa/family16kb/root_complex
-
Damien Zammit (Code Review)