Change in coreboot[master]: lenovo/g505s: properly program the IRQ tables - coreboot-gerrit

22 Nov 2020

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47852 )
Change subject: lenovo/g505s: properly program the IRQ tables
......................................................................
lenovo/g505s: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation,
just like the proper way done for asus/am1i-a AMD fam16h - closest
example for Lenovo G505S: all the fam15h boards have these "bad IRQs".
OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied:
* G505S boots fine to Linux - no angry IRQ-related messages at dmesg;
* KolibriOS sees 18 IRQs in a table and could successfully attach a
driver to Atheros QCA8172 onboard Ethernet controller with an IRQ 3.
Signed-off-by: Mike Banon mikebdp2@gmail.com
Change-Id: I3a3ca74ac0ae93606dab5d5333cb7a9d12a6b32f
---
M src/mainboard/lenovo/g505s/Kconfig
M src/mainboard/lenovo/g505s/acpi/routing.asl
M src/mainboard/lenovo/g505s/devicetree.cb
M src/mainboard/lenovo/g505s/irq_tables.c
M src/mainboard/lenovo/g505s/mainboard.c
M src/mainboard/lenovo/g505s/mptable.c
A src/mainboard/lenovo/g505s/mptable.h
7 files changed, 339 insertions(+), 393 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47852/1

diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig
index 322d3a7..75ae32c 100644
--- a/src/mainboard/lenovo/g505s/Kconfig
+++ b/src/mainboard/lenovo/g505s/Kconfig
@@ -11,6 +11,7 @@
    select DEFAULT_POST_ON_LPC
    select EC_COMPAL_ENE932
    select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
    select HAVE_MP_TABLE
    select HAVE_ACPI_RESUME
    select HAVE_SMI_HANDLER
@@ -47,4 +48,8 @@
    string
    default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS
+config IRQ_SLOT_COUNT
+	int
+	default 14
+
 endif # BOARD_LENOVO_G505S
diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl
index bf6a881..2c183a6 100644
--- a/src/mainboard/lenovo/g505s/acpi/routing.asl
+++ b/src/mainboard/lenovo/g505s/acpi/routing.asl
@@ -4,308 +4,170 @@
    Name(PR0, Package(){
    	/* NB devices */
    	/* Bus 0, Dev 0 - F15 Host Controller */
+		/* IOMMU:			0:02.00 - IRQ 3 */
    	Package(){0x0000FFFF, 0, INTA, 0 },
    	Package(){0x0000FFFF, 1, INTB, 0 },
    	Package(){0x0000FFFF, 2, INTC, 0 },
    	Package(){0x0000FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, INTB, 0 },
-		Package(){0x0001FFFF, 1, INTC, 0 },
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */
+		/* APU Integrated Graphics:	0:01.00 - IRQ 3 */
+		Package(){0x0001FFFF, 0, INTA, 0 },
+		/* APU HDMI Audio Controller:	0:01.01 - IRQ 4 */
+		Package(){0x0001FFFF, 1, INTB, 0 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		/* PCIe GPP to dGPU 1:00.00:	0:02.00 - IRQ 3 */
+		Package(){0x0002FFFF, 0, INTA, 0 },
+		Package(){0x0002FFFF, 1, INTB, 0 },
+		Package(){0x0002FFFF, 2, INTC, 0 },
+		Package(){0x0002FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */
+		/* PCIe GPP to Eth 2:00.00:	0:04.00 - IRQ 3 */
    	Package(){0x0004FFFF, 0, INTA, 0 },
    	Package(){0x0004FFFF, 1, INTB, 0 },
    	Package(){0x0004FFFF, 2, INTC, 0 },
    	Package(){0x0004FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */
+		/* PCIe GPP to WiFi 3:00.00:	0:05.00 - IRQ 4 */
    	Package(){0x0005FFFF, 0, INTB, 0 },
    	Package(){0x0005FFFF, 1, INTC, 0 },
    	Package(){0x0005FFFF, 2, INTD, 0 },
    	Package(){0x0005FFFF, 3, INTA, 0 },
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
+		/* SB devices */
+		/* USB XHCI:			0:10.00 - IRQ 5 */
+		Package(){0x0010FFFF, 0, INTC, 0 },
+		/* SATA:			0:11.00 - IRQ 7 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+		/* USB OHCI1:			0:12.00 - IRQ 5 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		/* USB EHCI1:			0:12.02 - IRQ 4 */
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		/* USB OHCI2:			0:13.00 - IRQ 5 */
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		/* USB EHCI2:			0:13.02 - IRQ 4 */
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		/* USB OHCI3:			0:16.00 - IRQ 5 */
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		/* USB EHCI3:			0:16.02 - IRQ 4 */
+		Package(){0x0016FFFF, 1, INTB, 0 },
    	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		/* Southbridge HD Audio:	0:14.02 - IRQ 3 */
    	Package(){0x0014FFFF, 0, INTA, 0 },
    	Package(){0x0014FFFF, 1, INTB, 0 },
+		/* USB OHCI4:			0:14.05 - IRQ 5 */
    	Package(){0x0014FFFF, 2, INTC, 0 },
    	Package(){0x0014FFFF, 3, INTD, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, INTC, 0 },
-		Package(){0x0010FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 21 PCIe Bridge */
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
    })
Name(APR0, Package(){
    	/* NB devices in APIC mode */
    	/* Bus 0, Dev 0 - F15 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, 0, 17 },
-		Package(){0x0001FFFF, 1, 0, 18 },
+		/* IOMMU:			0:02.00 - IRQ 3 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics (IGP) */
+		/* APU Integrated Graphics:	0:01.00 - IRQ 3 */
+		Package(){0x0001FFFF, 0, 0, 16 },
+		/* APU HDMI Audio Controller:	0:01.01 - IRQ 4 */
+		Package(){0x0001FFFF, 1, 0, 17 },
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		/* PCIe GPP to dGPU 1:00.00:	0:02.00 - IRQ 3 */
+		Package(){0x0002FFFF, 0, 0, 16 },
+		Package(){0x0002FFFF, 1, 0, 17 },
+		Package(){0x0002FFFF, 2, 0, 18 },
+		Package(){0x0002FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 4 - PCIe Bridge for x1 PCIe Slot */
+		/* PCIe GPP to Eth 2:00.00:	0:04.00 - IRQ 3 */
    	Package(){0x0004FFFF, 0, 0, 16 },
    	Package(){0x0004FFFF, 1, 0, 17 },
    	Package(){0x0004FFFF, 2, 0, 18 },
    	Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 5 - PCIe Bridge for x1 PCIe Slot */
+		/* PCIe GPP to WiFi 3:00.00:	0:05.00 - IRQ 4 */
    	Package(){0x0005FFFF, 0, 0, 17 },
    	Package(){0x0005FFFF, 1, 0, 18 },
    	Package(){0x0005FFFF, 2, 0, 19 },
    	Package(){0x0005FFFF, 3, 0, 16 },
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		Package(){0x0006FFFF, 0, 0, 18 },
-		Package(){0x0006FFFF, 1, 0, 19 },
-		Package(){0x0006FFFF, 2, 0, 16 },
-		Package(){0x0006FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		Package(){0x0007FFFF, 0, 0, 19 },
-		Package(){0x0007FFFF, 1, 0, 16 },
-		Package(){0x0007FFFF, 2, 0, 17 },
-		Package(){0x0007FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
+		/* SB devices in APIC mode */
+		/* USB XHCI:			0:10.00 - IRQ 5 */
+		Package(){0x0010FFFF, 0, 0, 18 },
+		/* SATA:			0:11.00 - IRQ 7 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+		/* USB OHCI1:			0:12.00 - IRQ 5 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		/* USB EHCI1:			0:12.02 - IRQ 4 */
+		Package(){0x0012FFFF, 1, 0, 17 },
+		/* USB OHCI2:			0:13.00 - IRQ 5 */
+		Package(){0x0013FFFF, 0, 0, 18 },
+		/* USB EHCI2:			0:13.02 - IRQ 4 */
+		Package(){0x0013FFFF, 1, 0, 17 },
+		/* USB OHCI3:			0:16.00 - IRQ 5 */
+		Package(){0x0016FFFF, 0, 0, 18 },
+		/* USB EHCI3:			0:16.02 - IRQ 4 */
+		Package(){0x0016FFFF, 1, 0, 17 },
    	/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		/* Southbridge HD Audio:	0:14.02 - IRQ 3 */
    	Package(){0x0014FFFF, 0, 0, 16 },
    	Package(){0x0014FFFF, 1, 0, 17 },
+		/* USB OHCI4:			0:14.05 - IRQ 5 */
    	Package(){0x0014FFFF, 2, 0, 18 },
    	Package(){0x0014FFFF, 3, 0, 19 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, 0, 0x12},
-		Package(){0x0010FFFF, 1, 0, 0x11},
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus0, Dev 21 PCIE Bridge */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
    })
Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
+		/* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
    })
    Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
+		/* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
    })
-
    Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
+		/* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */
    	Package(){0x0000FFFF, 0, INTA, 0 },
    	Package(){0x0000FFFF, 1, INTB, 0 },
    	Package(){0x0000FFFF, 2, INTC, 0 },
    	Package(){0x0000FFFF, 3, INTD, 0 },
    })
    Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
+		/* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */
    	Package(){0x0000FFFF, 0, 0, 16 },
    	Package(){0x0000FFFF, 1, 0, 17 },
    	Package(){0x0000FFFF, 2, 0, 18 },
    	Package(){0x0000FFFF, 3, 0, 19 },
    })
-
    Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
+		/* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */
    	Package(){0x0000FFFF, 0, INTB, 0 },
    	Package(){0x0000FFFF, 1, INTC, 0 },
    	Package(){0x0000FFFF, 2, INTD, 0 },
    	Package(){0x0000FFFF, 3, INTA, 0 },
    })
    Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
+		/* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */
    	Package(){0x0000FFFF, 0, 0, 17 },
    	Package(){0x0000FFFF, 1, 0, 18 },
    	Package(){0x0000FFFF, 2, 0, 19 },
    	Package(){0x0000FFFF, 3, 0, 16 },
    })
-
    Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
    })
    Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
    })
-
    Name(PS7, Package(){
-		/* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
    })
    Name(APS7, Package(){
-		/* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
    })
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 0*/
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 0*/
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 1*/
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 1*/
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 2*/
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 2*/
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 3 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 3*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	/* SB PCI Bridge J21, J22 */
    Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
    })
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 4b4df36..97254a5 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -41,7 +41,7 @@
    			end
    		end
    		device pci 14.4 on  end # FCH PCI Bridge [1022:780f]
-			device pci 14.5 off end # USB 2
+			device pci 14.5 on  end # USB 2
    		device pci 14.6 off end # Gec
    		device pci 14.7 off end # SD
    		device pci 15.0 off end # PCIe 0
diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c
index 0baf079..3898a72 100644
--- a/src/mainboard/lenovo/g505s/irq_tables.c
+++ b/src/mainboard/lenovo/g505s/irq_tables.c
@@ -1,88 +1,61 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <string.h>
-#include <stdint.h>
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,				/* u32 signature */
+	PIRQ_VERSION,				/* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
+	0x00,					/* Interrupt router bus */
+	(0x14 << 3) | 0x4,			/* Interrupt router dev */
+	0,					/* IRQs devoted exclusively to PCI usage */
+	0x1022,					/* Vendor */
+	0x780b,					/* Device */
+	0,					/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	/* u8 rfu[11] */
+	0x87,					/* Checksum (has to be set to some value that
+						* would give 0 after the sum of all bytes
+						* for this structure (including checksum).
+						*/
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		/* IOMMU:			0:02.00 - IRQ 3 */
+		{0x00, (0x00 << 3) | 0x2, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0},
+		/* APU Integrated Graphics:	0:01.00 - IRQ 3 */
+		/* APU HDMI Audio Controller:	0:01.01 - IRQ 4 */
+		{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* PCIe GPP to dGPU 1:00.00:	0:02.00 - IRQ 3 */
+		{0x00, (0x02 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0},
+		/* PCIe GPP to Eth 2:00.00:	0:04.00 - IRQ 3 */
+		{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0},
+		/* PCIe GPP to WiFi 3:00.00:	0:05.00 - IRQ 3 */
+		{0x00, (0x05 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0},
+		/* USB XHCI:			0:10.00 - IRQ 5 */
+		{0x00, (0x10 << 3) | 0x0, {{0x03, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* SATA:			0:11.00 - IRQ 7 */
+		{0x00, (0x11 << 3) | 0x0, {{0x04, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* USB OHCI1:			0:12.00 - IRQ 5 */
+		/* USB EHCI1:			0:12.02 - IRQ 4 */
+		{0x00, (0x12 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* USB OHCI2:			0:13.00 - IRQ 5 */
+		/* USB EHCI2:			0:13.02 - IRQ 4 */
+		{0x00, (0x16 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* USB OHCI3:			0:16.00 - IRQ 5 */
+		/* USB EHCI3:			0:16.02 - IRQ 4 */
+		{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x02, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000} }, 0x0, 0x0},
+		/* Southbridge HD Audio:	0:14.02 - IRQ 3 */
+		/* USB OHCI4:			0:14.05 - IRQ 5 */
+		{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x0, 0x0},
+		/* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */
+		{0x01, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x1, 0x0},
+		/* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */
+		{0x02, (0x00 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90} }, 0x2, 0x0},
+		/* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */
+		{0x03, (0x00 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90} }, 0x3, 0x0}
+	}
+};
unsigned long write_pirq_routing_table(unsigned long addr)
 {
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
 }
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
index d900c94..83e1f92 100644
--- a/src/mainboard/lenovo/g505s/mainboard.c
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -7,8 +7,56 @@
 #include <cpu/x86/smm.h>
 #include <device/device.h>
+#include <southbridge/amd/agesa/hudson/pci_devs.h>
+#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <northbridge/amd/agesa/family15tn/pci_devs.h>
 #include <southbridge/amd/agesa/hudson/smi.h>
+#include "mptable.h"
+
+/*
+ * This table defines the index into the picr/intr_data
+ * tables for each device.  Any enabled device and slot
+ * that uses hardware interrupts should have an entry
+ * in this table to define its index into the FCH
+ * PCI_INTR register 0xC00/0xC01.  This index will define
+ * the interrupt that it should use.  Putting PIRQ_A into
+ * the PIN A index for a device will tell that device to
+ * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+	/* {PCI_devfn,	{PIN A, PIN B, PIN C, PIN D} }, */
+	{IOMMU_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },		/* IOMMU:			0:02.00 - IRQ 3 */
+	{GFX_DEVFN,	{PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} },		/* APU Integrated Graphics:	0:01.00 - IRQ 3 */
+	{ACTL_DEVFN,	{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} },		/* APU HDMI Audio Controller:	0:01.01 - IRQ 4 */
+	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe GPP to dGPU 1:00.00:	0:02.00 - IRQ 3 */
+	{NB_PCIE_PORT3_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} },	/* PCIe GPP to Eth 2:00.00:	0:04.00 - IRQ 3 */
+	{NB_PCIE_PORT4_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} },	/* PCIe GPP to WiFi 3:00.00:	0:05.00 - IRQ 4 */
+	{XHCI_DEVFN,	{PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} },		/* USB XHCI:			0:10.00 - IRQ 5 */
+	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* SATA:			0:11.00 - IRQ 7 */
+	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* USB OHCI1:			0:12.00 - IRQ 5 */
+	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} },	/* USB EHCI1:			0:12.02 - IRQ 4 */
+	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* USB OHCI2:			0:13.00 - IRQ 5 */
+	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} },	/* USB EHCI2:			0:13.02 - IRQ 4 */
+	{OHCI3_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* USB OHCI3:			0:16.00 - IRQ 5 */
+	{EHCI3_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} },	/* USB EHCI3:			0:16.02 - IRQ 4 */
+	{HDA_DEVFN,	{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} },	/* Southbridge HD Audio:	0:14.02 - IRQ 3 */
+	{OHCI4_DEVFN,	{PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }	/* USB OHCI4:			0:14.05 - IRQ 5 */
+};
+
+const u8 *picr_data = mainboard_picr_data;
+const u8 *intr_data = mainboard_intr_data;
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	pirq_data_ptr = mainboard_pirq_data;
+	pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
 static void pavilion_cold_boot_init(void)
 {
    /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
@@ -21,6 +69,9 @@
 {
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
+
    hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
    global_smi_enable();
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index bc1759a..1c20d9b 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -5,24 +5,11 @@
 #include <arch/smp/mpspec.h>
 #include <stdint.h>
 #include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
+#include <drivers/generic/ioapic/chip.h>
-u8 picr_data[0x54] = {
-	0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x1F,0x1F,0x1F,0x1F
-};
-u8 intr_data[0x54] = {
-	0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	0x10,0x11,0x12,0x13
-};
+#include "mptable.h"
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {
@@ -56,114 +43,133 @@
    u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
    u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+	/* Initialize the MP_Table */
    mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
    memcpy(mc->mpc_oem, "AMD     ", 8);
+	/*
+	 * Type 0: Processor Entries:
+	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
+	 * CPU Signature (Stepping, Model, Family),
+	 * Feature Flags
+	 */
    smp_write_processors(mc);
-	//mptable_write_buses(mc, NULL, &bus_isa);
+	/*
+	 * Type 1: Bus Entries:
+	 * Bus ID, Bus Type
+	 */
+	// mptable_write_buses(mc, NULL, &bus_isa);
    my_smp_write_bus(mc, 0, "PCI   ");
    my_smp_write_bus(mc, 1, "PCI   ");
    bus_isa = 0x02;
    my_smp_write_bus(mc, bus_isa, "ISA   ");
-	/* I/O APICs:   APIC ID Version State   Address */
+	/*
+	 * Type 2: I/O APICs:
+	 * APIC ID, Version, APIC Flags:EN, Address
+	 */
    smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+	for (byte = 0x0; byte < sizeof(picr_data_ptr); byte++) {
    	outb(byte, 0xC00);
-		outb(picr_data[byte], 0xC01);
+		outb(mainboard_picr_data[byte], 0xC01);
    }
/* APIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+	for (byte = 0x0; byte < sizeof(intr_data_ptr); byte++) {
    	outb(byte | 0x80, 0xC00);
-		outb(intr_data[byte], 0xC01);
+		outb(mainboard_intr_data[byte], 0xC01);
    }
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	/*
+	 * Type 3: I/O Interrupt Table Entries:
+	 * Int Type, Int Polarity, Int Level, Source Bus ID,
+	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
+	 */
    mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
     * associated with a specific bus/device/function tuple.
     */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+#define PCI_INT(bus, dev, fn, pin) \
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-	/* IOMMU */
-	PCI_INT(0x0, 0x00, 0x0, 0x10);
-	PCI_INT(0x0, 0x00, 0x1, 0x11);
-	PCI_INT(0x0, 0x00, 0x2, 0x12);
-	PCI_INT(0x0, 0x00, 0x3, 0x13);
+	/* IOMMU:			0:02.00 - IRQ 3 */
+	PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]);
-	/* Internal VGA */
-	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Integrated Graphics:	0:01.00 - IRQ 3 */
+	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]);
+	/* APU HDMI Audio Controller:	0:01.01 - IRQ 4 */
+	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
-	/* SMBUS */
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* PCIe GPP to dGPU 1:00.00:	0:02.00 - IRQ 3 */
+	PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]);
+	/* PCIe GPP to Eth 2:00.00:	0:04.00 - IRQ 3 */
+	PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]);
+	/* PCIe GPP to WiFi 3:00.00:	0:05.00 - IRQ 4 */
+	PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]);
+	PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]);
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+	/* USB XHCI:			0:10.00 - IRQ 5 */
+	PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]);
+	/* SATA:			0:11.00 - IRQ 7 */
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
+	/* USB OHCI1:			0:12.00 - IRQ 5 */
+	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
+	/* USB EHCI1:			0:12.02 - IRQ 4 */
+	PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
+	/* USB OHCI2:			0:13.00 - IRQ 5 */
+	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
+	/* USB EHCI2:			0:13.02 - IRQ 4 */
+	PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
+	/* USB OHCI3:			0:16.00 - IRQ 5 */
+	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
+	/* USB EHCI3:			0:16.02 - IRQ 4 */
+	PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
+	/* Southbridge HD Audio:	0:14.02 - IRQ 3 */
+	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
+	/* USB OHCI4:			0:14.05 - IRQ 5 */
+	PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]);
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+	/* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */
+	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
-	/* sata */
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
-	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+	/* Onboard Ethernet (Eth) 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */
+	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]);
+	PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
-	/* on board NIC & Slot PCIE. */
+	/* PCIe x1 slot for WiFi 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */
+	PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]);
+	PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]);
+	PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]);
+	PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]);
-	/* PCI slots */
-	struct device *dev = pcidev_on_root(0x14, 4);
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+		smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin))
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/* PCIe Lan*/
-	PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-	/* FCH PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, 0x10);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, 0x11);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, 0x12);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
    /* There is no extension information... */
/* Compute the checksums */
diff --git a/src/mainboard/lenovo/g505s/mptable.h b/src/mainboard/lenovo/g505s/mptable.h
new file mode 100644
index 0000000..8e27e97
--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mptable.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms:
+ *
+ * SCI - System Controller Interrupt,
+ * SMBUS - System Management Bus,
+ * ASF - Advanced Synchronization Facility,
+ * HDA - HD Audio,
+ * SD - SD Flash Controller,
+ * GEC - Gigabit Ethernet Controller,
+ * PerMon - Performance Monitor,
+ * IMC - Integrated Memory Controller,
+ * GPP - PCIe General Purpose Ports.
+ */
+
+static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* Misc-nil,0,1,2, INTA-INTD from Serial irq */
+	[0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */
+	[0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F,
+	/* IMC INT0-INT5 */
+	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */
+	[0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05,
+	/* IDE, SATA */
+	[0x40] = 0x1F, 0x07,
+	/* GPP Int0-Int3 */
+	[0x50] = 0x1F, 0x1F, 0x1F, 0x1F
+};
+
+static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
+	/* INTA# - INTH# */
+	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* Misc-nil,0,1,2, INTA-INTD from Serial irq */
+	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */
+	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F,
+	/* IMC INT0-INT5 */
+	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	/* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */
+	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,
+	/* IDE, SATA */
+	[0x40] = 0x1F, 0x13,
+	/* GPP Int0-Int3 */
+	[0x50] = 0x1F, 0x1F, 0x1F, 0x1F
+};
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3a3ca74ac0ae93606dab5d5333cb7a9d12a6b32f
Gerrit-Change-Number: 47852
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon mikebdp2@gmail.com
Gerrit-MessageType: newchange



    