[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes

[Bill XIE (Code Review)]

Attention is currently required from: Angel Pons, Keith Hui.

Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )

Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
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Patch Set 3:

(1 comment)

File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:

https://review.coreboot.org/c/coreboot/+/85413/comment/7b208511_ace91943?usp... :
PS2, Line 77: {7, 34, 20, -1}
> Read your second dump. […]

pcie_port_coalesce is never enabled at build time in device tree of p8z77v, but it is enabled at runtime by southbridge/intel/bd82x6x/pch.c:pch_pcie_enable() when the first port is disabled, so disabling pcie_port_coalesce requires installing a device in the first port (PCIEX16_3).

However, the Marvell SATA card in PCIEX1_2 remains not detected.

autoport dump and cbmem log are here: https://send.aslaets.be/download/cfd69edaa438c656/#2u8w2MkLSdsePw5mZ3Xmdg , downloadable 5 times in 5 days.