[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8

[Sean Rhodes (Code Review)]

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Paul Menzel, Sean Rhodes.

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email )

Change subject: soc/intel/alderlake: Change the maximum C state to C8
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Patch Set 7:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84622/comment/29ce0e03_d2e2db23?usp... :
PS6, Line 9: Change the maximum C state allowed when S0ix isn't used to C8
           : to solve the following error:
           :     MWAIT C-state 0x33 not supported by HW (0x1010)
> Without reading the diff, I would have thought you decrease it from C10 or so to C8. […]

Done

https://review.coreboot.org/c/coreboot/+/84622/comment/807cddce_3c5588b6?usp... :
PS6, Line 11:     MWAIT C-state 0x33 not supported by HW (0x1010)
> Also, maybe say, that the error is shown because of the substate: […]

Google says the S is "Server Class"

https://review.coreboot.org/c/coreboot/+/84622/comment/eab82019_fdedba4c?usp... :
PS6, Line 13: Tested on `starbook_adl` with Ubuntu 24.04 by booting, and
            : performing multiple S3 cycles.
> Did you check with PowerTOP or turbostat if C8 was reached before and is now?

It is reached

File src/soc/intel/alderlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/84622/comment/b710f0e2_26ba5737?usp... :
PS6, Line 107: 	C_STATE_C8
> Also, excuse my ignorance, why can’t C10 be used? The page *Package C-States* [1] does not say anyth […]

AFAIK, it's just that you need S0ix enabled to reach C10 - oould be a specific reason, but it's not known to me!