Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31138
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31138/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index e54444a..c362e6c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -5,7 +5,6 @@ end
register "sci_irq" = "SCIS_IRQ10" - register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Disable all clkreq of PCIe root ports as SMARC interface do not # have this pins.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 1: Code-Review+1
Is this because of the APL47 errata listed on the spec update? (refer to Intel document number 334820, version 007)
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+1
Is this because of the APL47 errata listed on the spec update? (refer to Intel document number 334820, version 007)
Yes, that's exactly the problem.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@9 PS1, Line 9: Intel's faulty LPC clock Is that documented in some errata document?
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@12 PS1, Line 12: Tested how?
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 1: Code-Review+2
Hello Werner Zeh, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31138
to look at the new patch set (#2).
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31138/2
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@12 PS1, Line 12:
Tested how?
we have enabled the UPD data output for FSP-S via make menuconfig and checked the SirqMode offset
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31138/1//COMMIT_MSG@9 PS1, Line 9: Intel's faulty LPC clock
Is that documented in some errata document?
The one I listed. (which is now in the commit message)
I agree, it is not very detailed, but I investigated on the issue recently and saw correcting the SERIRQ mode is recommended. This is pretty similar to what killed the Bay-Trail C2000 series chips in many devices...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31138 )
Change subject: siemens/mc_apl2: Change SERIRQ mode ......................................................................
siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected. By removing this entry from devicetree, the default value (quiet mode) is used. The problem is described in Intel document 334820-007 under point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/31138 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Werner Zeh werner.zeh@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index e54444a..c362e6c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -5,7 +5,6 @@ end
register "sci_irq" = "SCIS_IRQ10" - register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Disable all clkreq of PCIe root ports as SMARC interface do not # have this pins.
-
Angel Pons (Code Review) -
Mario Scheithauer (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Werner Zeh (Code Review)