Change in coreboot[master]: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>"

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50229 )

Change subject: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>"
......................................................................

nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>"

This reverts commits

77d3b655ed nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>
  487c1a24f5 nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>
  875c21f491 nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>
  c4d1b47ad9 nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
  b96c358751 nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>
  9cbf26d18e nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The booblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: I562bf2cfd8c165338577a95c5c644cf5bea3a5c1
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/ironlake/bootblock.c
M src/northbridge/intel/sandybridge/bootblock.c
M src/northbridge/intel/x4x/bootblock.c
6 files changed, 14 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/50229/1

diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index e2cabdb..9c45f7e 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "gm45.h"
@@ -31,7 +31,7 @@
     * The PCIEXBAR is assumed to live in the memory mapped IO space under
     * 4GiB.
     */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
-	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
+	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg);
 }
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 0bb8ae2..64e2258 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
-
 #include "haswell.h"

static uint32_t encode_pciexbar_length(void)
@@ -29,7 +28,7 @@
     *
     * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
     */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
 }
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index edb9a8d..f4b4628 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
-
 #include "i945.h"

static uint32_t encode_pciexbar_length(void)
@@ -28,6 +27,6 @@
     *
     * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
     */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
+	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
 }
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 02b63a6..4b174cb 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
-
 #include "ironlake.h"

static uint32_t encode_pciexbar_length(void)
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 92f9aee..529f4f8 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -1,10 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>
-
 #include "sandybridge.h"

static uint32_t encode_pciexbar_length(void)
@@ -29,7 +28,7 @@
     *
     * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
     */
-	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
-	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
+	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
 }
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index aedcdd9..f15d181 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -2,8 +2,8 @@

#include <arch/bootblock.h>
 #include <arch/mmio.h>
-#include <arch/pci_io_cfg.h>
 #include <assert.h>
+#include <device/pci_ops.h>
 #include <types.h>

#include "x4x.h"