Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/21150 )

Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers
......................................................................

soc/intel/skylake: Usable dram top calculation based on HW registers

This patch ensures that entire system memory calculation is done
based on host bridge registers.

BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.

Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/skylake/memmap.c
2 files changed, 89 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21150/2