Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
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Patch Set 20:

(5 comments)

https://review.coreboot.org/#/c/27972/20/src/arch/riscv/fp_asm.S
File src/arch/riscv/fp_asm.S:

https://review.coreboot.org/#/c/27972/20/src/arch/riscv/fp_asm.S@27
PS20, Line 27: /* 
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https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@45
PS20, Line 45: /* opcode/mask used to identify instruction, 
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https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@47
PS20, Line 47: 	uint32_t opcode; 
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https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@142
PS20, Line 142: 	for(i = 0; i < ARRAY_SIZE(insn_info); i++)
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https://review.coreboot.org/#/c/27972/20/src/arch/riscv/misaligend.c@143
PS20, Line 143: 		if((insn_info[i].mask & insn) == insn_info[i].opcode)
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