Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29014
Change subject: amd/stoneyridge: Rename GppClkCntrl fields ......................................................................
amd/stoneyridge: Rename GppClkCntrl fields
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file.
Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/mainboard/google/kahlee/mainboard.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29014/1
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index bfd1f2f..ebdcc93 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -146,15 +146,15 @@
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK2_CLOCK_REQ_MAP_MASK, - GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 << - GPP_CLK2_CLOCK_REQ_MAP_SHIFT); + GPP_CLK2_REQ_MAP_MASK, + GPP_CLK2_REQ_MAP_CLK_REQ2 << + GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK0_CLOCK_REQ_MAP_MASK, - GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 << - GPP_CLK0_CLOCK_REQ_MAP_SHIFT); + GPP_CLK0_REQ_MAP_MASK, + GPP_CLK0_REQ_MAP_CLK_REQ0 << + GPP_CLK0_REQ_MAP_SHIFT); }
/************************************************* diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d25c90b..7f02811 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -111,13 +111,13 @@
/* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0 -#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8 -#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT) -#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3 +#define GPP_CLK2_REQ_MAP_SHIFT 8 +#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) +#define GPP_CLK2_REQ_MAP_CLK_REQ2 3
-#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0 -#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT) -#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1 +#define GPP_CLK0_REQ_MAP_SHIFT 0 +#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) +#define GPP_CLK0_REQ_MAP_CLK_REQ0 1
#define MISC_CGPLL_CONFIG1 0x08 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)