Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 )

Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
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Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@7 
PS3, Line 7: nem
> NEM

Done

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@12 
PS3, Line 12: upto
> up to

Done

https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 
PS3, Line 20: 
            : Also the COS mask selection is mapped to bit 32:33 of MSR
            : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before
            : MSR write instead of eax(mas 31:0). This implementation corrects that
            : as well.
> Gotcha, thanks Aamir, I am finding the documentation around this register kind of confusing 😕

for CNL, SKL and KBL i could check the mask selection is mapped to LSB.

For JSL it is documented in doc#618876 chapter 50.