Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
superio/nuvoton/nct6779d: Open some LDN config registers
The porting of Asus P8Z77-M mainboard required changing certain Super I/O configuration registers that was ignored in devicetree.cb because it isn't listed as a resource. Add the declaration so they can be changed.
This change is nowhere near enough as the current structure is insufficient to allow changing configuration registers in the 0xE? range, which this board also needed.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 is reflected when inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2 Signed-off-by: Keith Hui buurin@gmail.com --- M src/superio/nuvoton/nct6779d/superio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41226/1
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 9eff320..327ef10 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -38,8 +38,8 @@ { NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, }, { NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, NCT6779D_ACPI}, - { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + { NULL, NCT6779D_ACPI, PNP_MSC2,}, + { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, 0x0ffe, 0x0ffe, }, { NULL, NCT6779D_WDT1}, { NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, @@ -52,8 +52,8 @@ { NULL, NCT6779D_GPIO2}, { NULL, NCT6779D_GPIO3}, { NULL, NCT6779D_GPIO4}, - { NULL, NCT6779D_GPIO5}, - { NULL, NCT6779D_GPIO6}, + { NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5}, + { NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5}, { NULL, NCT6779D_GPIO7}, { NULL, NCT6779D_GPIO8}, };
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
Patch Set 1: Code-Review+2
(4 comments)
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@10 PS1, Line 10: was were
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@11 PS1, Line 11: it isn't listed as a resource they aren't listed as resources
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@16 PS1, Line 16: needed needs
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@18 PS1, Line 18: is are
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has uploaded a new patch set (#2) to the change originally created by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
superio/nuvoton/nct6779d: Open some LDN config registers
The porting of Asus P8Z77-M mainboard required changing certain Super I/O configuration registers that were ignored in devicetree.cb because they aren't listed as resources. Add the declaration so they can be changed.
This change is nowhere near enough as the current structure is insufficient to allow changing configuration registers in the 0xE? range, which this board also needs.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2 Signed-off-by: Keith Hui buurin@gmail.com --- M src/superio/nuvoton/nct6779d/superio.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41226/2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@10 PS1, Line 10: was
were
Done
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@11 PS1, Line 11: it isn't listed as a resource
they aren't listed as resources
Done
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@16 PS1, Line 16: needed
needs
Done
https://review.coreboot.org/c/coreboot/+/41226/1//COMMIT_MSG@18 PS1, Line 18: is
are
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
superio/nuvoton/nct6779d: Open some LDN config registers
The porting of Asus P8Z77-M mainboard required changing certain Super I/O configuration registers that were ignored in devicetree.cb because they aren't listed as resources. Add the declaration so they can be changed.
This change is nowhere near enough as the current structure is insufficient to allow changing configuration registers in the 0xE? range, which this board also needs.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2 Signed-off-by: Keith Hui buurin@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/superio/nuvoton/nct6779d/superio.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 843857c..ef50aa6 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -37,8 +37,8 @@ { NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, }, { NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, NCT6779D_ACPI}, - { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + { NULL, NCT6779D_ACPI, PNP_MSC2,}, + { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, 0x0ffe, 0x0ffe, }, { NULL, NCT6779D_WDT1}, { NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, @@ -51,8 +51,8 @@ { NULL, NCT6779D_GPIO2}, { NULL, NCT6779D_GPIO3}, { NULL, NCT6779D_GPIO4}, - { NULL, NCT6779D_GPIO5}, - { NULL, NCT6779D_GPIO6}, + { NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5}, + { NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5}, { NULL, NCT6779D_GPIO7}, { NULL, NCT6779D_GPIO8}, };
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41226 )
Change subject: superio/nuvoton/nct6779d: Open some LDN config registers ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4664 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4663 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4662 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4661
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Felix Held (Code Review)
-
Keith Hui (Code Review)
-
Patrick Georgi (Code Review)