Lee Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16005
-gerrit
commit 24b6dad2268ca6fd79bfb763753d46e275bcebec Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Jul 31 13:40:15 2016 -0700
soc/intel/quark: Disable FSP serial output
Add a Kconfig value to enable FSP serial output. By default, this Kconfig value is not selected. Use this Kconfig value to determine if the serial port address is passed to FSP instead of NULL.
TEST=Build and run on Galileo Gen2.
Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/Kconfig | 6 ++++++ src/soc/intel/quark/romstage/fsp1_1.c | 3 ++- src/soc/intel/quark/romstage/fsp2_0.c | 3 ++- 3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index c1a35b2..0a9df97 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -225,6 +225,12 @@ config FSP_S_FILE depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/FSP_S.fd"
+config FSP_ENABLE_SERIAL_OUTPUT + bool "Should FSP use the debug serial port?" + default n + help + When selected enables FSP to write to the debug serial port. + ##### # RMU binary # The following options control the Quark chipset microcode file diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index 73910a0..483cef9 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -112,7 +112,8 @@ void soc_memory_init_params(struct romstage_params *params, upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = IS_ENABLED(CONFIG_FSP_ENABLE_SERIAL_OUTPUT) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 6d4267b..b2ebd69 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -162,7 +162,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = IS_ENABLED(CONFIG_FSP_ENABLE_SERIAL_OUTPUT) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal;
-
Lee Leahy