Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25600 )
Change subject: nb/intel/i945: Use parallel MP init ......................................................................
nb/intel/i945: Use parallel MP init
Use the parallel mp init path to initialize AP's. This should result in a moderate speedup.
Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is 26ms faster compared to lapic_cpu_init.
This removes the option to disable HT siblings.
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/25600 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/Makefile.inc M src/cpu/intel/model_f4x/model_f4x_init.c M src/mainboard/apple/macbook21/cmos.default M src/mainboard/apple/macbook21/cmos.layout M src/mainboard/asus/p5gc-mx/cmos.default M src/mainboard/asus/p5gc-mx/cmos.layout M src/mainboard/getac/p470/cmos.layout M src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default M src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout M src/mainboard/ibase/mb899/cmos.layout M src/mainboard/intel/d945gclf/cmos.default M src/mainboard/intel/d945gclf/cmos.layout M src/mainboard/kontron/986lcd-m/cmos.layout M src/mainboard/lenovo/t60/cmos.default M src/mainboard/lenovo/t60/cmos.layout M src/mainboard/lenovo/x60/cmos.default M src/mainboard/lenovo/x60/cmos.layout M src/mainboard/lenovo/z61t/cmos.default M src/mainboard/lenovo/z61t/cmos.layout M src/mainboard/roda/rk886ex/cmos.layout M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/northbridge.c M src/southbridge/intel/i82801gx/lpc.c 29 files changed, 22 insertions(+), 61 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 0703099..eec544d 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -2,5 +2,6 @@ subdirs-y += ../../x86/name subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index a609aed..24a9ad2 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -85,15 +85,18 @@ x86_enable_cache();
/* Update the microcode */ - intel_update_microcode_from_cbfs(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_update_microcode_from_cbfs();
/* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
/* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) { + x86_setup_mtrrs(); + x86_mtrr_check(); + }
/* Enable the local CPU APICs */ setup_lapic(); @@ -110,7 +113,8 @@ /* TODO: PIC thermal sensor control */
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 13e08f0..46ae7c7 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -2,5 +2,6 @@ subdirs-y += ../../x86/name subdirs-y += ../common subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-y += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 78ece74..72a259d 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -18,11 +18,8 @@ #include <device/device.h> #include <string.h> #include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/hyperthreading.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -118,17 +115,10 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Update the microcode */ - intel_update_microcode_from_cbfs(); - /* Print processor name */ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Setup MTRRs */ - x86_setup_mtrrs(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
@@ -146,9 +136,6 @@
/* PIC thermal sensor control */ configure_pic_thermal_sensors(); - - /* Start up my CPU siblings */ - intel_sibling_init(cpu); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 7367914..19b2e93 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_f3x_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index b71e279..fc0db17 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -24,7 +24,7 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -37,7 +37,8 @@ setup_lapic();
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 2f11d7f..6fbc9ae 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += model_f4x_init.c subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 +ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index a5322d7..1b3cfe9 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -24,7 +24,7 @@ /* Turn on caching if we haven't already */ x86_enable_cache();
- if (!intel_ht_sibling()) { + if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { /* MTRRs are shared between threads */ x86_setup_mtrrs(); x86_mtrr_check(); @@ -37,7 +37,8 @@ setup_lapic();
/* Start up my CPU siblings */ - intel_sibling_init(cpu); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + intel_sibling_init(cpu); };
static struct device_operations cpu_dev_ops = { diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index ad126ca..cf1bc456 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' boot_default=0x40 diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 554d608..39bf608 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -53,7 +53,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/asus/p5gc-mx/cmos.default b/src/mainboard/asus/p5gc-mx/cmos.default index 2cb37df..e842a7d 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.default +++ b/src/mainboard/asus/p5gc-mx/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' gfx_uma_size=8M diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index 4ca560c..187b910 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -31,7 +31,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index f054851..fd627a5 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -53,7 +53,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default index 2cb37df..e842a7d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' gfx_uma_size=8M diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout index bdc264b..881fd41 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -52,7 +52,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index 5b1799b..daa2999 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -52,7 +52,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/intel/d945gclf/cmos.default b/src/mainboard/intel/d945gclf/cmos.default index 2cb37df..e842a7d 100644 --- a/src/mainboard/intel/d945gclf/cmos.default +++ b/src/mainboard/intel/d945gclf/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' gfx_uma_size=8M diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index bdc264b..881fd41 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -52,7 +52,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index dfa0cad..135c19a 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -52,7 +52,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index d6479af..af865f1 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' boot_default=0x41 diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index fd6b25f..d7ff0f2 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -69,7 +69,6 @@ #938 7 r 0 unused
# coreboot config options: cpu -944 1 e 2 hyper_threading #945 3 r 0 unused
# coreboot config options: ec diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index f17d57c..5c3576d 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' boot_default=0x40 diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index b5a31ca..bfc78bc 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -69,7 +69,6 @@ #938 6 r 0 unused
# coreboot config options: cpu -944 1 e 2 hyper_threading #945 4 r 0 unused
# coreboot config options: ec diff --git a/src/mainboard/lenovo/z61t/cmos.default b/src/mainboard/lenovo/z61t/cmos.default index d6479af..af865f1 100644 --- a/src/mainboard/lenovo/z61t/cmos.default +++ b/src/mainboard/lenovo/z61t/cmos.default @@ -1,6 +1,5 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable nmi=Enable boot_devices='' boot_default=0x41 diff --git a/src/mainboard/lenovo/z61t/cmos.layout b/src/mainboard/lenovo/z61t/cmos.layout index bb3b94a..b9e2b44 100644 --- a/src/mainboard/lenovo/z61t/cmos.layout +++ b/src/mainboard/lenovo/z61t/cmos.layout @@ -68,7 +68,6 @@ #938 7 r 0 unused
# coreboot config options: cpu -944 1 e 2 hyper_threading #945 3 r 0 unused
# coreboot config options: ec diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 618745a..57ffa43 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -53,7 +53,6 @@ #399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading #401 7 r 0 unused
# coreboot config options: southbridge diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 92bf652..996e1d9 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -30,6 +30,7 @@ select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 10a7ba4..7c209dc 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -165,26 +165,6 @@ pci_write_config8(dev, SMRAM, smram); }
-/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -249,7 +229,7 @@
static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); }
static struct device_operations cpu_bus_ops = { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index b20b2aa..5ad05c7 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -353,7 +353,8 @@ /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ - smm_lock(); + if (!IS_ENABLED(CONFIG_PARALLEL_MP)) + smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */
-
Patrick Georgi (Code Review)