Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 )
Change subject: soc/mediatek/mt8195: fix GPIO register offsets
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55163/comment/5beb661c_0ac6047f
PS1, Line 9: Fix GPIO pu/pd offset.
Thanks. Please put this in commit description […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/55163/comment/7025b8c2_cf9a6172
PS4, Line 7: soc/mediatek/mt8195: fix GPIO register offset
Plural: offsets?
Done
https://review.coreboot.org/c/coreboot/+/55163/comment/ee8d0d0c_cec7bd7a
PS4, Line 10:
Where did you get the new values from? Did something not work before and works now?
I add document info in commit message.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/55163
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9b0f8a24756092a97933cc9d4ba13a9e79c73e91
Gerrit-Change-Number: 55163
Gerrit-PatchSet: 5
Gerrit-Owner: Rex-BC Chen
rex-bc.chen@mediatek.corp-partner.google.com
Gerrit-Reviewer: Hung-Te Lin
hungte@chromium.org
Gerrit-Reviewer: Yu-Ping Wu
yupingso@google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@mailbox.org
Gerrit-Attention: Hung-Te Lin
hungte@chromium.org
Gerrit-Attention: Paul Menzel
paulepanter@mailbox.org
Gerrit-Attention: Yu-Ping Wu
yupingso@google.com
Gerrit-Comment-Date: Fri, 04 Jun 2021 06:33:25 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Hung-Te Lin
hungte@chromium.org
Comment-In-Reply-To: Rex-BC Chen
rex-bc.chen@mediatek.corp-partner.google.com
Comment-In-Reply-To: Paul Menzel
paulepanter@mailbox.org
Gerrit-MessageType: comment