[S] Change in coreboot[main]: soc/intel/meteorlake: Move CNVi control out of chipset.cb

[Sean Rhodes (Code Review)]

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86088?usp=email )

Change subject: soc/intel/meteorlake: Move CNVi control out of chipset.cb
......................................................................

soc/intel/meteorlake: Move CNVi control out of chipset.cb

Not every board will use CNVi, so move this out of the chipset.cb
and into devicetree.

Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1
Signed-off-by: Sean Rhodes 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86088
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
M src/mainboard/system76/mtl/devicetree.cb
M src/soc/intel/meteorlake/chipset.cb
5 files changed, 7 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved

diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
index bdebde5..19eb34e 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -1,4 +1,6 @@
 chip soc/intel/meteorlake
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"

# GPE configuration
    register "pmc_gpe0_dw0" = "GPP_D"
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 55de7d2..04b7cf6 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -1,4 +1,6 @@
 chip soc/intel/meteorlake
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"

# GPE configuration
    register "pmc_gpe0_dw0" = "GPP_B"
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 45c8f0b..d4f2ea3 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -9,6 +9,8 @@
 end

chip soc/intel/meteorlake
+	# Enable CNVi WiFi
+	register "cnvi_wifi_core" = "true"

# GPE configuration
    register "pmc_gpe0_dw0" = "GPP_B"
diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb
index 0e1eaac..899788d 100644
--- a/src/mainboard/system76/mtl/devicetree.cb
+++ b/src/mainboard/system76/mtl/devicetree.cb
@@ -34,6 +34,7 @@
    	device ref ioe_shared_sram on end
    	device ref pmc_shared_sram on end
    	device ref cnvi_wifi on
+			register "cnvi_wifi_core" = "true"
    		register "cnvi_bt_core" = "true"
    		register "cnvi_bt_audio_offload" = "true"
    		chip drivers/wifi/generic
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 865b3d0..9087dd8 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -29,9 +29,6 @@
    # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
    register "tcc_offset" = "20"

-	# Enable CNVi WiFi
-	register "cnvi_wifi_core" = "true"
-
    device domain 0 on
    	device pci 00.0 alias system_agent on end
    	device pci 01.0 alias pcie_rp12 off end