[S] Change in coreboot[master]: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

[Bora Guvendik (Code Review)]

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik.

Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Jérémy Compostella, Bora Guvendik,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/70165

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode
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soc/intel/alderlake: Disable L1 substates for PCIe compliance test mode

Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings

Signed-off-by: Bora Guvendik 
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70165/2