[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable

[Reagan (Code Review)]

Attention is currently required from: Angel Pons, Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford.

Reagan has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )

Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
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Patch Set 2:

(1 comment)

File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/eefaa8af_8ff6976f?usp... :
PS2, Line 190: 		device ref pcie_rp1	on  end
> The PCI specification says that multi-function devices must always implement function 0. To provide flexibility, Intel allows remapping PCH PCIe root port functions so that root port 1 doesn't have to be enabled when it's not in use.
> IIRC, it's because a PCI device has to have a function 0 so it can be enumerated. If the root port corresponding to function 0 isn't enabled, the PCH promotes the first enabled function to function 0.

Thank you both, that makes sense.

Changing `pcie_rp1` to `pcie_rp3` works fine on my variant. As for the other board, I assume that's the case too, considering `PcieRpEnable` is enabled for 3, but not 1; I believe `pcie_rp1` could be removed entirely, but I am not an expert here by any definition. Booting with the stock firmware also does not create a root port 1.