[XS] Change in coreboot[main]: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5 - coreboot-gerrit

31 May 2024


      Attention is currently required from: Jeremy Soller, Paul Menzel.
Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75283?usp=email )
Change subject: lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
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Patch Set 3: Code-Review+2
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
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Gerrit-Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87
Gerrit-Change-Number: 75283
Gerrit-PatchSet: 3
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