[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size

[Krystian Hebel (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Michał Żygowski, Nico Huber.

Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................

Patch Set 10:

(1 comment)

File src/device/pciexp_device.c:

https://review.coreboot.org/c/coreboot/+/77338/comment/eba3fd7f_325a4ee2 :
PS10, Line 645: 	pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap);
IIUC this limits max payload size just for the device immediately above current one, how does it work if there are more bridges along the way?

Also, PCIe specifications describes special treatment of ARI devices, i.e. only Function 0 of such device should be considered.