[M] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87027?usp=email )
Change subject: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants ......................................................................
mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants
This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE ports. The variants files structure is inspired by system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board and the new cw-adlnth-1c2l-v3.0 (named according to original bios naming).
CPU: Intel N100 or N305 Memory: 1x DDR5-4800 SODIMM (max 16 GB) NIC: 2x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 2x Ethernet - 2x HDMI - 2x USB 2.0
Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - 1x HDMI - 2x Intel I226 2.5 GbE NICs - M.2 ports - ACPI S3 - Fan (ITE IT8613E) driver IT87 (frankcrawford github fork)
Not tested: - The second HDMI - Audio - S0ix (cw-adl-4l-v1.0 said it's not working) - Internal USB ports
VBT extracted from vendor UEFI firmware version F2 (2024-06-26 10:26:38) was 100% matching the cw-adl-4l-v1.0, so we kept only one in the tree.
Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Signed-off-by: Julian Intronati julian.intronati@eho.link Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027 Reviewed-by: Julian Intronati julian.intronati@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/cwwk/adl/Kconfig M src/mainboard/cwwk/adl/Kconfig.name M src/mainboard/cwwk/adl/Makefile.mk M src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/include/mainboard/gpio.h R src/mainboard/cwwk/adl/ramstage.c A src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt R src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c R src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c A src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt C src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c A src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c 12 files changed, 110 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Julian Intronati: Looks good to me, but someone else must approve
diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig index c8dbd04..11b8e3c 100644 --- a/src/mainboard/cwwk/adl/Kconfig +++ b/src/mainboard/cwwk/adl/Kconfig @@ -1,8 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
-if BOARD_CWWK_ADL_N - -config BOARD_SPECIFIC_OPTIONS +config BOARD_CWWK_ADL_N_COMMON def_bool y select BOARD_ROMSIZE_KB_16384 select CRB_TPM @@ -15,11 +13,36 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SUPERIO_ITE_IT8613E
+config BOARD_CWWK_CW_ADL_4L_V1 + select BOARD_CWWK_ADL_N_COMMON + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + select BOARD_CWWK_ADL_N_COMMON + +if BOARD_CWWK_ADL_N_COMMON + config MAINBOARD_DIR default "cwwk/adl"
+config VARIANT_DIR + default "cw-adl-4l-v1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "cw-adlntb-1c2l-v3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + config MAINBOARD_PART_NUMBER - default "CW-AL-4L-V1.0" + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-X86-P5-V3" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_VERSION + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
config NO_POST default y diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name index 7faa8e4..d102e32 100644 --- a/src/mainboard/cwwk/adl/Kconfig.name +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later
-config BOARD_CWWK_ADL_N +config BOARD_CWWK_CW_ADL_4L_V1 bool "CW-ADL-4L-V1.0" + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + bool "CW-ADLNTB-1C2L-V3.0" diff --git a/src/mainboard/cwwk/adl/Makefile.mk b/src/mainboard/cwwk/adl/Makefile.mk index 89eb072db..432208b 100644 --- a/src/mainboard/cwwk/adl/Makefile.mk +++ b/src/mainboard/cwwk/adl/Makefile.mk @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c
-romstage-y += romstage_fsp_params.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c
-ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt index b53863c..7166620 100644 --- a/src/mainboard/cwwk/adl/board_info.txt +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: CWWK -Board name: CW-ADL-4L-V1.0 Category: eval +ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/cwwk/adl/include/mainboard/gpio.h b/src/mainboard/cwwk/adl/include/mainboard/gpio.h new file mode 100644 index 0000000..ef2a21c --- /dev/null +++ b/src/mainboard/cwwk/adl/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/ramstage.c similarity index 71% rename from src/mainboard/cwwk/adl/mainboard.c rename to src/mainboard/cwwk/adl/ramstage.c index b15d017..fb968e1 100644 --- a/src/mainboard/cwwk/adl/mainboard.c +++ b/src/mainboard/cwwk/adl/ramstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <mainboard/gpio.h> #include <soc/ramstage.h> -#include "gpio.h"
static void mainboard_init(void *chip_info) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); }
struct chip_operations mainboard_ops = { diff --git a/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt new file mode 100644 index 0000000..5eba41c --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-ADL-4L-V1.0 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c similarity index 98% rename from src/mainboard/cwwk/adl/gpio.h rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c index fc3d7ea..0223539 100644 --- a/src/mainboard/cwwk/adl/gpio.h +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef CFG_GPIO_H -#define CFG_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h>
/* Pad configuration was generated automatically using intelp2m utility */ @@ -294,4 +292,7 @@ PAD_NC(GPP_R7, NONE), /* GPIO */ };
-#endif /* CFG_GPIO_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c similarity index 100% rename from src/mainboard/cwwk/adl/romstage_fsp_params.c rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt new file mode 100644 index 0000000..e466a7a --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-X86-P5-V3 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c similarity index 90% copy from src/mainboard/cwwk/adl/gpio.h copy to src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c index fc3d7ea..ab16207 100644 --- a/src/mainboard/cwwk/adl/gpio.h +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef CFG_GPIO_H -#define CFG_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h>
/* Pad configuration was generated automatically using intelp2m utility */ @@ -25,7 +23,7 @@ //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ - PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ PAD_NC(GPP_B15, NONE), /* GPIO */ PAD_NC(GPP_B16, NONE), /* GPIO */ PAD_NC(GPP_B17, NONE), /* GPIO */ @@ -65,14 +63,14 @@ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_A8, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), /* GPIO */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ - PAD_NC(GPP_A11, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */ PAD_NC(GPP_A12, NONE), /* GPIO */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ PAD_NC(GPP_A14, NONE), /* GPIO */ - PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), /* GPIO */ PAD_NC(GPP_A16, NONE), /* GPIO */ PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ @@ -119,9 +117,9 @@
/* ------- GPIO Group GPP_H ------- */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ - PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 1, PLTRST), /* GPIO */ PAD_NC(GPP_H4, NONE), /* GPIO */ PAD_NC(GPP_H5, NONE), /* GPIO */ PAD_NC(GPP_H6, NONE), /* GPIO */ @@ -129,7 +127,7 @@ PAD_NC(GPP_H8, NONE), /* GPIO */ PAD_NC(GPP_H9, NONE), /* GPIO */ PAD_NC(GPP_H10, NONE), /* GPIO */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H11, NONE), /* GPIO */ PAD_NC(GPP_H12, NONE), /* GPIO */ PAD_NC(GPP_H13, NONE), /* GPIO */ PAD_NC(GPP_H14, NONE), /* GPIO */ @@ -137,7 +135,7 @@ PAD_NC(GPP_H16, NONE), /* GPIO */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H19, NONE), /* GPIO */ PAD_NC(GPP_H20, NONE), /* GPIO */ PAD_NC(GPP_H21, NONE), /* GPIO */ PAD_NC(GPP_H22, NONE), /* GPIO */ @@ -145,7 +143,7 @@
/* ------- GPIO Group GPP_D ------- */ PAD_NC(GPP_D0, NONE), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ PAD_NC(GPP_D2, NONE), /* GPIO */ PAD_NC(GPP_D3, NONE), /* GPIO */ PAD_NC(GPP_D4, NONE), /* GPIO */ @@ -155,10 +153,10 @@ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ - PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPIO */ PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ - PAD_NC(GPP_D13, NONE), /* GPIO */ - PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPIO */ PAD_NC(GPP_D15, NONE), /* GPIO */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ PAD_NC(GPP_D17, NONE), /* GPIO */ @@ -173,12 +171,12 @@ /* ------- GPIO Group GPP_GPD ------- */ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ - PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_GPO(GPD2, 1, DEEP), /* GPIO */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ - PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ @@ -255,14 +253,14 @@ PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */
/* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* GPIO */ PAD_NC(GPP_E1, NONE), /* GPIO */ PAD_NC(GPP_E2, NONE), /* GPIO */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ - PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPIO */ PAD_NC(GPP_E5, NONE), /* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ - PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ PAD_NC(GPP_E8, NONE), /* GPIO */ PAD_NC(GPP_E9, NONE), /* GPIO */ PAD_NC(GPP_E10, NONE), /* GPIO */ @@ -273,10 +271,10 @@ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ PAD_NC(GPP_E17, NONE), /* GPIO */ - PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */ - PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */ - PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E18, NATIVE), /* GPIO */ + PAD_NC(GPP_E19, NATIVE), /* GPIO */ + PAD_NC(GPP_E20, NONE), /* GPIO */ + PAD_NC(GPP_E21, NONE), /* GPIO */ PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ @@ -294,4 +292,7 @@ PAD_NC(GPP_R7, NONE), /* GPIO */ };
-#endif /* CFG_GPIO_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c new file mode 100644 index 0000000..cd32138 --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x52, }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +}
-
Felix Held (Code Review)