Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43807 )
Change subject: nb/intel/haswell: Add RMRR for USB devices ......................................................................
nb/intel/haswell: Add RMRR for USB devices
FIXME: Figure out which address the RMRR corresponds to.
VT-d checklist verifies that there's a RMRR entry for USB devices. If said devices are enabled, add the RMRR entry.
Tested on Asrock B85M Pro4, verify VT-d check about USB RMRR passes.
Change-Id: I800d6d1847f457827d64b39c5b7bbfc9cb04f230 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43807/1
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 6a6a124..5e28c82 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -87,7 +87,7 @@ acpi_dmar_drhd_fixup(tmp, current); }
- return current; + return acpi_create_usb_rmrr(current); }
unsigned long northbridge_write_acpi_tables(const struct device *const dev, diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index 8fee16b..6a2103b 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -77,3 +77,36 @@ ssdt->length = current - (unsigned long)ssdt; ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); } + +unsigned long acpi_create_usb_rmrr(const unsigned long tmp) +{ + unsigned long current = tmp; + + struct device *const ehc1_dev = pcidev_on_root(0x1d, 0); + struct device *const ehc2_dev = pcidev_on_root(0x1a, 0); + struct device *const xhci_dev = pcidev_on_root(0x14, 0); + + const bool ehc1_enabled = ehc1_dev && ehc1_dev->enabled; + const bool ehc2_enabled = ehc2_dev && ehc2_dev->enabled; + const bool xhci_enabled = xhci_dev && xhci_dev->enabled; + + /* If no USB devices are enabled, do not generate the RMRR entry */ + if (!ehc1_enabled && !ehc2_enabled && !xhci_enabled) + return current; + + /* FIXME: This should be the address of the runtime register space instead! */ + current += acpi_create_dmar_rmrr(current, 0, 0x3e2e0000, 0x3e300000 - 1); + + if (ehc1_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1d, 0); + + if (ehc2_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x1a, 0); + + if (xhci_enabled) + current += acpi_create_dmar_ds_pci(current, 0, 0x14, 0); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..79d9dbc 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -122,6 +122,8 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
+unsigned long acpi_create_usb_rmrr(const unsigned long tmp); + void enable_usb_bar(void); int early_pch_init(void); void pch_enable_lpc(void);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43807 )
Change subject: nb/intel/haswell: Add RMRR for USB devices ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43807/1/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/acpi.c:
https://review.coreboot.org/c/coreboot/+/43807/1/src/southbridge/intel/lynxp... PS1, Line 97: FIXME FIXME. Any suggestions? We don't configure that...
Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43807 )
Change subject: nb/intel/haswell: Add RMRR for USB devices ......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/lynxpoint/acpi.c:
https://review.coreboot.org/c/coreboot/+/43807/comment/936b7ab4_2751eba0 PS1, Line 97: FIXME
FIXME. Any suggestions? We don't configure that...
These numbers are mentioned in the SA BIOS Spec as an example mentioning that things could be done very differently. So I assume it's really just about DRAM that a BIOS would choose for DMA. And thus of no concern for coreboot.
Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43807 )
Change subject: nb/intel/haswell: Add RMRR for USB devices ......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/lynxpoint/acpi.c:
https://review.coreboot.org/c/coreboot/+/43807/comment/34796dfe_feb24914 PS1, Line 97: FIXME
These numbers are mentioned in the SA BIOS Spec as an example mentioning […]
Ack
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43807 )
Change subject: nb/intel/haswell: Add RMRR for USB devices ......................................................................
Abandoned
Nonsense
-
Angel Pons (Code Review) -
Nico Huber (Code Review)