Change in coreboot[master]: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed
Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39452 )
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
soc/intel/*/smihandler: Only compile in TCO SMI handler if needed
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case.
Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 5 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39452/1
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 53d2b7e..0e55cb3 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -49,7 +49,9 @@ [APM_SMI_STS] = smihandler_southbridge_apmc, [FAKE_PM1_SMI_STS] = smihandler_southbridge_pm1, [GPIO_SMI_STS] = smihandler_southbridge_gpi, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_SMI_STS] = smihandler_southbridge_tco, +#endif [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4d0b241..de42e77 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -123,7 +123,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index b7c37d4..ed09749 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -120,7 +120,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 2e93075..0729f7b 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -63,7 +63,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index bf07bea..e58b590 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -120,7 +120,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, };
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39452 )
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
Patch Set 1: Code-Review+2
Hello Aaron Durbin, Michael Niewöhner, Andrey Petrov, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39452
to look at the new patch set (#2).
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
soc/intel/*/smihandler: Only compile in TCO SMI handler if needed
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case.
Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 5 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/39452/2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39452 )
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
Patch Set 2: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39452 )
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39452 )
Change subject: soc/intel/*/smihandler: Only compile in TCO SMI handler if needed ......................................................................
soc/intel/*/smihandler: Only compile in TCO SMI handler if needed
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case.
Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi pgeorgi@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Michael Niewöhner --- M src/soc/intel/apollolake/smihandler.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/smihandler.c M src/soc/intel/tigerlake/smihandler.c 5 files changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index e37de92..073d665 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -39,7 +39,9 @@ [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, [GPIO_STS_BIT] = smihandler_southbridge_gpi, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4be7897..f68f4c2 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -48,7 +48,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 6be7b70..ec9deb2 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -46,7 +46,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 4818c02..213de0a 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -26,7 +26,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 0e8d345..1eb56aa 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -46,7 +46,9 @@ [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, };
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Aaron Durbin (Code Review) -
Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)