Change in coreboot[master]: mb/asus/p8z77: Use native ram init and depricate mrc.bin code
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54336 )
Change subject: mb/asus/p8z77: Use native ram init and depricate mrc.bin code ......................................................................
mb/asus/p8z77: Use native ram init and depricate mrc.bin code
Signed-off-by: Bill XIE persmule@hardenedlinux.org Change-Id: I79dc64c25cb36c630bf9994bf04a0dfe8654eb3c --- M src/mainboard/asus/p8x7x/Kconfig M src/mainboard/asus/p8x7x/cmos.default M src/mainboard/asus/p8x7x/cmos.layout M src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c 4 files changed, 45 insertions(+), 214 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/54336/1
diff --git a/src/mainboard/asus/p8x7x/Kconfig b/src/mainboard/asus/p8x7x/Kconfig index e6e9bf7..4cfd3c4 100644 --- a/src/mainboard/asus/p8x7x/Kconfig +++ b/src/mainboard/asus/p8x7x/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_LIBGFXINIT select INTEL_GMA_HAVE_VBT select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT # for ASM1061 eSATA select DRIVERS_ASMEDIA_ASPM_BLACKLIST if BOARD_ASUS_P8Z77_M_PRO
diff --git a/src/mainboard/asus/p8x7x/cmos.default b/src/mainboard/asus/p8x7x/cmos.default index 6811b0b..c7aa620 100644 --- a/src/mainboard/asus/p8x7x/cmos.default +++ b/src/mainboard/asus/p8x7x/cmos.default @@ -1,11 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only - boot_option=Fallback debug_level=Debug -gfx_uma_size=224M -nmi=Enable +nmi=Disable +power_on_after_fail=Disable sata_mode=AHCI -#usb3_xxxx options are only used with MRC blob, ignored else -usb3_mode=Enable -usb3_drv=Enable -usb3_streams=Enable +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x/cmos.layout b/src/mainboard/asus/p8x7x/cmos.layout index 3d717b4..0f9de5e 100644 --- a/src/mainboard/asus/p8x7x/cmos.layout +++ b/src/mainboard/asus/p8x7x/cmos.layout @@ -8,60 +8,24 @@
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option +384 1 e 2 boot_option 388 4 h 0 reboot_counter
# ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +395 4 e 3 debug_level
-# ----------------------------------------------------------------- # coreboot config options: southbridge - -# Non Maskable Interrupt(NMI) support, which is an interrupt that may -# occur on a RAM or unrecoverable error. 408 1 e 1 nmi
-409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode
-# ----------------------------------------------------------------- # coreboot config options: northbridge +416 5 e 6 gfx_uma_size
-# gfx_uma_size -# Quantity of shared video memory the IGP can use -# -416 5 e 7 gfx_uma_size - -# ----------------------------------------------------------------- -# coreboot config options: usb3 - -# usb3_mode -# Controls how the motherboard's USB3 ports act at boot time -421 2 e 8 usb3_mode - -# usb3_drv -# Load (or not) pre-OS xHCI USB3 BIOS driver -# -423 1 e 1 usb3_drv - -# usb3_streams -# Streams can provide more speed (as they can use 64Kb packets), -# but they might cause incompatibilities with some devices. -# -424 1 e 1 usb3_streams - -# ----------------------------------------------------------------- -# Sandy/Ivy Bridge MRC Scrambler Seed values -# note: MUST NOT be covered by checksum! -464 32 r 0 mrc_scrambler_seed -496 32 r 0 mrc_scrambler_seed_s3 -528 16 r 0 mrc_scrambler_seed_chk - -# ----------------------------------------------------------------- # coreboot config options: check sums -544 16 h 0 check_sum +984 16 h 0 check_sum
# -----------------------------------------------------------------
@@ -73,78 +37,50 @@ 1 1 Enable
# boot_option -3 0 Fallback -3 1 Normal +2 0 Fallback +2 1 Normal
# debug_level -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew
# power_on_after_fail -5 0 Disable -5 1 Enable -5 2 Keep +4 0 Disable +4 1 Enable +4 2 Keep
# sata_mode -6 0 AHCI -6 1 Compatible +5 0 AHCI +5 1 Compatible +5 2 Legacy
# gfx_uma_size (Intel IGP Video RAM size) -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M -7 7 256M -7 8 288M -7 9 320M -7 10 352M -7 11 384M -7 12 416M -7 13 448M -7 14 480M -7 15 512M -7 16 544M -7 17 576M -7 18 608M -7 19 640M -7 20 672M -7 21 704M -7 22 736M -7 23 768M -7 24 800M -7 25 832M -7 26 864M -7 27 896M -7 28 928M -7 29 960M -7 30 992M - -# usb3_mode -# Disable = Use the port always as USB 2.0 for compatibility -# Enable = Use the port always as USB 3.0 for speed -# Auto = Initialize the port as USB 2.0, until the OS loads -# xHCI USB 3.0 driver -# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver -# and the computer is reset, keep the USB 3.0 mode. -# -8 0 Disable -8 1 Enable -8 2 Auto -8 3 SmartAuto +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M
# ----------------------------------------------------------------- -# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> -# <bit where to start storing checksum[must be 16bits-aligned]> checksums
-checksum 392 431 544 +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c index 78ad877..a6916c2 100644 --- a/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x/variants/z77-m_pro/early_init.c @@ -53,104 +53,3 @@ read_spd(&spd[2], 0x52, id_only); read_spd(&spd[3], 0x53, id_only); } - -int mainboard_should_reset_usb(int s3resume) -{ - return !s3resume; -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - /* - * USB3 mode: - * 0 = Disable: work always as USB 2.0(ehci) - * 1 = Enable: work always as USB 3.0(xhci) - * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver - * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver - * and reboots, it will keep the USB3.0 speed - */ - unsigned int usb3_mode = get_uint_option("usb3_mode", 1); - usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */ - - /* Load USB3 pre-OS xHCI driver */ - unsigned int usb3_drv = get_uint_option("usb3_drv", 1); - usb3_drv &= 0x1; /* ensure it's 0/1 only */ - - /* Use USB3 xHCI streams */ - unsigned int usb3_streams = get_uint_option("usb3_streams", 1); - usb3_streams &= 0x1; /* ensure it's 0/1 only */ - - struct pei_data pd = { - .pei_version = PEI_VERSION, - .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE, - .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE, - .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */ - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */ - .gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */ - .max_ddr3_freq = 1600, /* 1333=Sandy; 1600=Ivy */ - .usb_port_config = { - /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 0, 0x0080 }, /* USB3 front internal header */ - { 1, 1, 0x0080 }, /* USB3 ETH top connector */ - { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ - { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 3, 0x0080 }, /* USB2 internal header (USB78) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 4, 0x0080 }, /* USB2 internal header (USB910) */ - { 1, 6, 0x0080 }, /* USB2 internal header (USB1112) */ - { 1, 5, 0x0080 }, /* USB2 internal header (USB1112) */ - { 0, 5, 0x0080 }, /* Unused. Asus DEBUG_PORT ??? */ - { 0, 6, 0x0080 } /* Unused. Asus DEBUG_PORT ??? */ - }, - .usb3 = { - /* 0=Disable; 1=Enable (start at USB3 speed) - * 2=Auto (start as USB2 speed until OS loads) - * 3=Smart Auto (like Auto but keep speed on reboot) - */ - usb3_mode, - /* 4 bit switch mask. 0=not switchable, 1=switchable - * Means once it's loaded the OS, it can swap ports - * from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - */ - 0xf, - usb3_drv, /* 1=Load xHCI pre-OS drv */ - /* 0=Don't use xHCI streams for better compatibility - * 1=use xHCI streams for better speed - */ - usb3_streams - }, - /* ASUS P8Z77-M PRO manual says 1.35v DIMMs are supported */ - .ddr3lv_support = 1, - /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, - * but might cause some system instability ! - */ - .pcie_init = 1, - /* Command Rate. 0=Auto; 1=1N; 2=2N. - * Leave it always at Auto for compatibility & stability - */ - .nmode = 0, - /* DDR refresh rate. 0=Auto based on DRAM's temperature; - * 1=Normal rate for speed; 2=Double rate for stability - */ - .ddr_refresh_rate_config = 0 - }; - - /* copy the data to output PEI */ - *pei_data = pd; -}
-
Bill XIE (Code Review)