Change in coreboot[master]: soc/intel/common: Prevent SMI storm when setting SPI WPD bit

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Patrick Rudolph, Benjamin Doron, Tim Wawrzynczak.
Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50754

to look at the new patch set (#4).

Change subject: soc/intel/common: Prevent SMI storm when setting SPI WPD bit
......................................................................

soc/intel/common: Prevent SMI storm when setting SPI WPD bit

From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMM handler, which results in a deadlock.

Avoid deadlocks by clearing the SPI status bits in the SMM handler. This
patch does not handle eSPI because I cannot test it, and knowing whether
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).

Tested on out-of-tree HP 280 G2, no longer deadlocks when using SMM BIOS
write protection. However, write protection is still not being enforced.

Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons 
---
M src/soc/intel/common/block/fast_spi/fast_spi.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/common/block/smm/smihandler.c
3 files changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/50754/4