Change in coreboot[master]: soc/intel/xeon_sp: Move set_bios_init_completion() - coreboot-gerrit

3 Nov 2020

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47172 )
Change subject: soc/intel/xeon_sp: Move set_bios_init_completion()
......................................................................
soc/intel/xeon_sp: Move set_bios_init_completion()
Move set_bios_init_completion() and helper functions from skx
and cpx soc_util.c to xeon common util.c. There are some slight
differences between skx and cpx, so used the more correct cpx
functions. Both cpx and skx platforms boot as expected.
Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Signed-off-by: Marc Jones marcjones@sysproconsulting.com
---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/util.c
7 files changed, 137 insertions(+), 253 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47172/1

diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 0049616..3daff13 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -12,6 +12,7 @@
 #include <soc/cpu.h>
 #include <soc/ramstage.h>
 #include <soc/soc_util.h>
+#include <soc/util.h>
/* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
index 8c454bb2..649e6b5 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h
@@ -15,7 +15,8 @@
const struct SystemMemoryMapHob *get_system_memory_map(void);
-void set_bios_init_completion(void);
+uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+
 int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 149f2c0..973d258 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
-#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <intelblocks/cpulib.h>
@@ -11,7 +10,6 @@
 #include <soc/util.h>
 #include <stdlib.h>
 #include <string.h>
-#include <timer.h>
const struct SystemMemoryMapHob *get_system_memory_map(void)
 {
@@ -54,50 +52,7 @@
    return hob->PlatformData.Pci64BitResourceAllocation;
 }
-/* return true if command timed out else false */
-static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
-	uint32_t target)
-{
-	const uint32_t max_delay = 5000; /* 5 seconds max */
-	const uint32_t step_delay = 50; /* 50 us */
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, max_delay);
-	while ((pci_s_read_config32(dev, reg) & mask) != target) {
-		udelay(step_delay);
-		if (stopwatch_expired(&sw)) {
-			printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, "
-				"mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
-			return true; /* timedout */
-		}
-	}
-	return false; /* successful */
-}
-
-/* return true if command timed out else false */
-static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
-{
-	/* verify bios is not in busy state */
-	if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
-		return true; /* timed out */
-
-	/* write data to data register */
-	printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
-		PCU_CR1_BIOS_MB_DATA_REG, data);
-	pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
-
-	/* write the command */
-	printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
-		PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
-	pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
-		command | BIOS_MB_RUN_BUSY_MASK);
-
-	/* wait for completion or time out*/
-	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
-		BIOS_MB_RUN_BUSY_MASK, 0);
-}
-
-static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
+uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 {
    const IIO_UDS *hob = get_iio_uds();
@@ -106,88 +61,6 @@
    return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase;
 }
-/* return true if command timed out else false */
-static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
-	uint32_t pcode_init_mask, uint32_t val)
-{
-	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
-	uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
-	reg &= (uint32_t) ~rst_cpl_mask;
-	reg |= val;
-
-	/* update BIOS RESET completion bit */
-	pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
-
-	/* wait for PCU ack */
-	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
-		pcode_init_mask);
-}
-
-static void set_bios_init_completion_for_package(uint32_t socket)
-{
-	uint32_t data;
-	bool timedout;
-	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
-	/* read PCU config */
-	timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
-	if (timedout) {
-		/* 2nd try */
-		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
-		if (timedout)
-			die("BIOS PCU Misc Config Read timed out.\n");
-
-		/* Since the 1st try failed, we need to make sure PCU is in stable state */
-		data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
-		printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n",
-			__func__, PCU_CR1_BIOS_MB_DATA_REG, data);
-		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
-		if (timedout)
-			die("BIOS PCU Misc Config Write timed out.\n");
-	}
-
-	/* update RST_CPL3, PCODE_INIT_DONE3 */
-	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
-		PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
-	if (timedout)
-		die("BIOS RESET CPL3 timed out.\n");
-
-	/* update RST_CPL4, PCODE_INIT_DONE4 */
-	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
-		PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
-	if (timedout)
-		die("BIOS RESET CPL4 timed out.\n");
-
-	/* set CSR_DESIRED_CORES_CFG2 lock bit */
-	data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
-	data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
-	printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
-		__func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
-	pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
-}
-
-void set_bios_init_completion(void)
-{
-	/* FIXME: This may need to be changed for multi-socket platforms */
-	uint32_t sbsp_socket_id = 0;
-
-	/*
-	 * According to the BIOS Writer's Guide, the SBSP must be the last socket
-	 * to receive the BIOS init completion message. So, we send it to all non-SBSP
-	 * sockets first.
-	 */
-	for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) {
-		if (socket == sbsp_socket_id)
-			continue;
-		set_bios_init_completion_for_package(socket);
-	}
-
-	/* And finally, take care of the SBSP */
-	set_bios_init_completion_for_package(sbsp_socket_id);
-}
 /*
  * EX: CPX-SP
  * Ports    Stack   Stack(HOB)  IioConfigIou
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index 73fc63d..014b238 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -15,5 +15,6 @@
 const IIO_UDS *get_iio_uds(void);
 unsigned int soc_get_num_cpus(void);
 void xeonsp_init_cpu_config(void);
+void set_bios_init_completion(void);
#endif
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
index fd0d4e2..b42aec0 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
@@ -17,7 +17,8 @@
const struct SystemMemoryMapHob *get_system_memory_map(void);
-void set_bios_init_completion(void);
+uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
+
 int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 3faaed0..469fd60 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -2,7 +2,6 @@
#include <assert.h>
 #include <console/console.h>
-#include <delay.h>
 #include <device/pci.h>
 #include <hob_iiouds.h>
 #include <intelblocks/cpulib.h>
@@ -14,7 +13,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/soc_util.h>
 #include <soc/util.h>
-#include <timer.h>
/*
@@ -83,51 +81,7 @@
    return hob->PlatformData.Pci64BitResourceAllocation;
 }
-/* return 1 if command timed out else 0 */
-static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
-	uint32_t target)
-{
-	uint32_t max_delay = 5000; /* 5 seconds max */
-	uint32_t step_delay = 50; /* 50 us */
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, max_delay);
-	while ((pci_mmio_read_config32(dev, reg) & mask) != target) {
-		udelay(step_delay);
-		if (stopwatch_expired(&sw)) {
-			printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, "
-				"mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
-			return 1; /* timedout */
-		}
-	}
-	return 0; /* successful */
-}
-
-/* return 1 if command timed out else 0 */
-static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
-{
-	/* verify bios is not in busy state */
-	if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
-		return 1; /* timed out */
-
-	/* write data to data register */
-	printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
-				 PCU_CR1_BIOS_MB_DATA_REG, data);
-	pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
-
-	/* write the command */
-	printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
-		PCU_CR1_BIOS_MB_INTERFACE_REG,
-		(uint32_t) (command | BIOS_MB_RUN_BUSY_MASK));
-	pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
-		(uint32_t) (command | BIOS_MB_RUN_BUSY_MASK));
-
-	/* wait for completion or time out*/
-	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
-		BIOS_MB_RUN_BUSY_MASK, 0);
-}
-
-static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
+uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
 {
    size_t hob_size;
    const IIO_UDS *hob;
@@ -141,82 +95,6 @@
    return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
 }
-/* return 1 if command timed out else 0 */
-static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
-	uint32_t pcode_init_mask, uint32_t val)
-{
-	uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-	pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
-	uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
-	reg &= (uint32_t) ~rst_cpl_mask;
-	reg |= rst_cpl_mask;
-	reg |= val;
-
-	/* update BIOS RESET completion bit */
-	pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
-
-	/* wait for PCU ack */
-	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
-		pcode_init_mask);
-}
-
-static void set_bios_init_completion_for_package(uint32_t socket)
-{
-	uint32_t data;
-	uint32_t timedout;
-	uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
-	pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
-	/* read pcu config */
-	timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
-	if (timedout) {
-		/* 2nd try */
-		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
-		if (timedout)
-			die("BIOS PCU Misc Config Read timed out.\n");
-
-		data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
-		printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n",
-			__func__, PCU_CR1_BIOS_MB_DATA_REG, data);
-
-		/* write PCU config */
-		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
-		if (timedout)
-			die("BIOS PCU Misc Config Write timed out.\n");
-	}
-
-	/* update RST_CPL3, PCODE_INIT_DONE3 */
-	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
-		PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
-	if (timedout)
-		die("BIOS RESET CPL3 timed out.\n");
-
-	/* update RST_CPL4, PCODE_INIT_DONE4 */
-	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
-		PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
-	if (timedout)
-		die("BIOS RESET CPL4 timed out.\n");
-	/* set CSR_DESIRED_CORES_CFG2 lock bit */
-	data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
-	data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
-	printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
-		__func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
-	pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
-}
-
-void set_bios_init_completion(void)
-{
-	uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */
-
-	for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
-		if (socket == sbsp_socket_id)
-			continue;
-		set_bios_init_completion_for_package(socket);
-	}
-	set_bios_init_completion_for_package(sbsp_socket_id);
-}
-
 void config_reset_cpl3_csrs(void)
 {
    uint32_t data, plat_info, max_min_turbo_limit_ratio;
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index feacca4..2eaf6bf 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -3,12 +3,15 @@
 #include <assert.h>
 #include <commonlib/sort.h>
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <intelblocks/cpulib.h>
 #include <soc/pci_devs.h>
 #include <soc/msr.h>
+#include <soc/soc_util.h>
 #include <soc/util.h>
+#include <timer.h>
void get_stack_busnos(uint32_t *bus)
 {
@@ -221,4 +224,130 @@
    	++num_apics;
    }
 }
+
+/* return true if command timed out else false */
+static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
+	uint32_t target)
+{
+	const uint32_t max_delay = 5000; /* 5 seconds max */
+	const uint32_t step_delay = 50; /* 50 us */
+	struct stopwatch sw;
+
+	stopwatch_init_msecs_expire(&sw, max_delay);
+	while ((pci_s_read_config32(dev, reg) & mask) != target) {
+		udelay(step_delay);
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, "
+				"mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
+			return true; /* timedout */
+		}
+	}
+	return false; /* successful */
+}
+
+/* return true if command timed out else false */
+static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
+{
+	/* verify bios is not in busy state */
+	if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
+		return true; /* timed out */
+
+	/* write data to data register */
+	printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
+		PCU_CR1_BIOS_MB_DATA_REG, data);
+	pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
+
+	/* write the command */
+	printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
+		PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
+	pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
+		command | BIOS_MB_RUN_BUSY_MASK);
+
+	/* wait for completion or time out*/
+	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
+		BIOS_MB_RUN_BUSY_MASK, 0);
+}
+
+/* return true if command timed out else false */
+static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
+	uint32_t pcode_init_mask, uint32_t val)
+{
+	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
+
+	uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
+	reg &= (uint32_t) ~rst_cpl_mask;
+	reg |= val;
+
+	/* update BIOS RESET completion bit */
+	pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
+
+	/* wait for PCU ack */
+	return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
+		pcode_init_mask);
+}
+
+static void set_bios_init_completion_for_package(uint32_t socket)
+{
+	uint32_t data;
+	bool timedout;
+	const uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
+	const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
+
+	/* read PCU config */
+	timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+	if (timedout) {
+		/* 2nd try */
+		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+		if (timedout)
+			die("BIOS PCU Misc Config Read timed out.\n");
+
+		/* Since the 1st try failed, we need to make sure PCU is in stable state */
+		data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
+		printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n",
+			__func__, PCU_CR1_BIOS_MB_DATA_REG, data);
+		timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
+		if (timedout)
+			die("BIOS PCU Misc Config Write timed out.\n");
+	}
+
+	/* update RST_CPL3, PCODE_INIT_DONE3 */
+	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
+		PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
+	if (timedout)
+		die("BIOS RESET CPL3 timed out.\n");
+
+	/* update RST_CPL4, PCODE_INIT_DONE4 */
+	timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
+		PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
+	if (timedout)
+		die("BIOS RESET CPL4 timed out.\n");
+
+	/* set CSR_DESIRED_CORES_CFG2 lock bit */
+	data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
+	data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
+	printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
+		__func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
+	pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
+}
+
+void set_bios_init_completion(void)
+{
+	/* FIXME: This may need to be changed for multi-socket platforms */
+	uint32_t sbsp_socket_id = 0;
+
+	/*
+	 * According to the BIOS Writer's Guide, the SBSP must be the last socket
+	 * to receive the BIOS init completion message. So, we send it to all non-SBSP
+	 * sockets first.
+	 */
+	for (uint32_t socket = 0; socket < soc_get_num_cpus(); ++socket) {
+		if (socket == sbsp_socket_id)
+			continue;
+		set_bios_init_completion_for_package(socket);
+	}
+
+	/* And finally, take care of the SBSP */
+	set_bios_init_completion_for_package(sbsp_socket_id);
+}
 #endif
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/47172
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Gerrit-Change-Number: 47172
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones marc@marcjonesconsulting.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-MessageType: newchange



    