Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer

[Angel Pons (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, EricR Lai.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 )

Change subject: soc/intel/alderlake: Add support for external clock buffer
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/50162/comment/2a741d67_84680289 
PS1, Line 9: 3 CLKSRC using external clock buffer.
           : CLKSRC 6 provides feed clock to discrete buffer for further
           : distribution to platform.
> @Furquan, you can looks into 2 things […]

Hmmm... If I understand correctly, these SRCCLK_OE#7-9 signals are outputs from ADL-P and are routed to input pins on the external clock buffer chip. And these signals allow the ADL-P iSClk to control the CLKSRC outputs on the external clock chip. Thus, we can think of the external clock buffer chip as an extension of the PCH iSClk, and we have to tell FSP about it.

If the previous paragraph is true, then we can simply treat the CLKSRCs from the external clock buffer chip as if they came out of the PCH. I would adapt the Kconfig options as follows:

config PCIE_GEN3_EXTERNAL_CLOCK_BUFFER
    def_bool n
    depends on !SOC_INTEL_ALDERLAKE_PCH_M
    help
      Mainboard has an external PCIe Gen3 clock chip for ADL-P. SRC 6 provides
      feed clock to discrete buffer for further distribution to platform.

config MAX_PCIE_CLOCK_SRC
    int
    default 10 if PCIE_GEN3_EXTERNAL_CLOCK_BUFFER
    default 6  if SOC_INTEL_ALDERLAKE_PCH_M
    default 7

config MAX_PCIE_CLOCK_REQ
    int
    default 10 if PCIE_GEN3_EXTERNAL_CLOCK_BUFFER
    default 6  if SOC_INTEL_ALDERLAKE_PCH_M
    default 7