Change in coreboot[master]: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58740 )

Change subject: mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
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mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree

On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 12 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mario Scheithauer: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index f6ac8b7..e96e654 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -53,19 +53,19 @@
    register "PcieRpEnable[3]" = "1"
    register "PcieRpEnable[6]" = "1"

-	register "PcieClkSrcUsage[0]" = "0x00"
-	register "PcieClkSrcUsage[1]" = "0x01"
-	register "PcieClkSrcUsage[2]" = "0x02"
-	register "PcieClkSrcUsage[3]" = "0xFF"
-	register "PcieClkSrcUsage[4]" = "0xFF"
-	register "PcieClkSrcUsage[5]" = "0xFF"
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"

-	register "PcieClkSrcClkReq[0]" = "0xFF"
-	register "PcieClkSrcClkReq[1]" = "0xFF"
-	register "PcieClkSrcClkReq[2]" = "0xFF"
-	register "PcieClkSrcClkReq[3]" = "0xFF"
-	register "PcieClkSrcClkReq[4]" = "0xFF"
-	register "PcieClkSrcClkReq[5]" = "0xFF"
+	register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"

# Disable all L1 substates for PCIe root ports
    register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"