Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46275 )
Change subject: cpu/intel/common: rework AES-NI locking ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/common... File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/common... PS6, Line 286: msr_set
msr_set_bit ?
Done
https://review.coreboot.org/c/coreboot/+/46275/6/src/cpu/intel/common/common... PS6, Line 286: AESNI_LOCK
then this would still need to be zero (not 1<<0), msr_set_bits takes a bit index and does the shifti […]
you missed CB:46354 ;)
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.h File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46275/4/src/include/cpu/intel/msr.h... PS4, Line 9: (1 << 0)
How about `BIT(0)` ? (would require #include <types. […]
we shouldn't mix it; this is the way it's done most of the times in headers; see x86/msr.h for example or intelblocks/msr.h
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Michael Niewöhner (Code Review)