Patch set updated for coreboot: a2db755 intel/i945: Only write CID, PN, TCID, and ULBA once

[Mono Moosbart]

Mono Moosbart ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5387

-gerrit

commit a2db75519444c5056a0eeb8ad12cf23b49c2bbc8
Author: Mono 
Date:   Sat Mar 15 21:27:18 2014 +0100

intel/i945: Only write CID, PN, TCID, and ULBA once

Component ID (CID) in Element Self Description Register (ESD)
    can be written once only. The current implementation tries
    to write CID three times. The second and third write operations
    have no effect. Moreover, the current implementation does not
    make sure the read-only bits remain unchanged.

The same is true for Target Port Number (PN) and
    Target Component ID (TCID) in Upstream Link Descriptor Register (ULD).
    The current implementation tries to write those bits twice. The second
    operation is ignored.

Upstream Link Base Address Register (ULBA) is affected too.

Change-Id: Iea731951af2411cbada77ccdcaacca239e4ffdc6
    Signed-off-by: Mono 
---
 src/northbridge/intel/i945/early_init.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 57232af..47b8afc 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -310,7 +310,6 @@ static void ich7_setup_dmi_rcrb(void)

RCBA32(V0CTL) = 0x80000001;
    RCBA32(V1CAP) = 0x03128010;
-	RCBA32(ESD) = 0x00000810;
    RCBA32(RP1D) = 0x01000003;
    RCBA32(RP2D) = 0x02000002;
    RCBA32(RP3D) = 0x03000002;
@@ -332,12 +331,6 @@ static void ich7_setup_dmi_rcrb(void)
    reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
    RCBA32(V1CTL) = reg32;

-	RCBA32(ESD) |= (2 << 16);
-
-	RCBA32(ULD) |= (1 << 24) | (1 << 16);
-
-	RCBA32(ULBA) = DEFAULT_DMIBAR;
-
    RCBA32(RP1D) |= (2 << 16);
    RCBA32(RP2D) |= (2 << 16);
    RCBA32(RP3D) |= (2 << 16);
@@ -845,10 +838,14 @@ static void i945_setup_root_complex_topology(void)

static void ich7_setup_root_complex_topology(void)
 {
-	RCBA32(0x104) = 0x00000802;
-	RCBA32(0x110) = 0x00000001;
+	/* Component ID (CID), Write-Once bit */
+	RCBA32(ESD) |= (2 << 16);
+	/* Target Port Number (PN) and Target Component ID (TCID), Write-Once bits */
+	RCBA32(ULD) |= (1 << 24) | (1 << 16);
+	/* What is this? */
    RCBA32(0x114) = 0x00000000;
-	RCBA32(0x118) = 0x00000000;
+	/* Upstream Link Base Address Register (ULBA), Write-Once register */
+	RCBA32(ULBA) = DEFAULT_DMIBAR;
 }

static void ich7_setup_pci_express(void)