Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

[Furquan Shaikh (Code Review)]

Attention is currently required from: Krishna P Bhat D.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 )

Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
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Patch Set 5: Code-Review+1

(1 comment)

Patchset:

PS5: 
LGTM. I will let Karthik +2 this.