Change in coreboot[master]: mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot

[Timothy Pearson (Code Review)]

Timothy Pearson has uploaded a new change for review. ( https://review.coreboot.org/19820 )

Change subject: mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot
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mb/asus/kgpe-d16: Set ASpeed GPIO SPD mux lines during boot

When the BMC firmware module is installed on the KGPE-D16, the
RAM SPD multiplexer lines are disconnected by hardware from the
SP5100 GPIOs and attached to BMC GPIO lines instead.

Set the BMC GPIOs to match the state of the SP5100 GPIOs during
RAM setup.

Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5
Signed-off-by: Timothy Pearson 
---
M src/mainboard/asus/kgpe-d16/romstage.c
1 file changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/19820/1

diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 9459d6c..a486a10 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -87,6 +87,47 @@
    byte &= ~0xc0;			/* Enable SPD mux GPIO output drivers */
    byte |= (channel << 2) & 0xc;	/* Set SPD mux GPIOs */
    pci_write_config8(PCI_DEV(0, 0x14, 0), 0x54, byte);
+
+	/* Temporary AST PCI mapping */
+	uint32_t base_memory = 0xfc000000;
+	uint32_t memory_limit = 0xfc800000;
+
+	/* Temporarily enable the SP5100 PCI bridge */
+	uint16_t prev_sec_cfg = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x04);
+	uint8_t prev_sec_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x19);
+	uint8_t prev_sec_sub_bus = pci_read_config8(PCI_DEV(0, 0x14, 4), 0x1a);
+	uint16_t prev_sec_mem_base = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x20);
+	uint16_t prev_sec_mem_limit = pci_read_config16(PCI_DEV(0, 0x14, 4), 0x22);
+	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, 0x01);
+	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, 0xff);
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, (base_memory >> 20));
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, (memory_limit >> 20));
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, 0x2);
+
+	/* Temporarily enable AST BAR1 */
+	uint32_t prev_ast_cfg = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x04);
+	uint32_t prev_ast_bar1 = pci_read_config32(PCI_DEV(1, 0x1, 0), 0x14);
+	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, base_memory);
+	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, 0x02100002);
+
+	/* Use the P2A bridge to set ASpeed SPD mux GPIOs to the same values as the SP5100 */
+	void* ast_bar1 = (void*)base_memory;
+	write32(ast_bar1 + 0xf004, 0x1e780000);								/* Enable access to GPIO controller */
+	write32(ast_bar1 + 0xf000, 0x1);
+	write32(ast_bar1 + 0x10024, read32(ast_bar1 + 0x10024) | 0x3000);				/* Enable SPD mux GPIO output drivers */
+	write32(ast_bar1 + 0x10020, (read32(ast_bar1 + 0x10020) & ~0x3000) | ((channel & 0x3) << 12));	/* Set SPD mux GPIOs */
+	write32(ast_bar1 + 0xf000, 0x0);
+
+	/* Deconfigure AST BAR1 */
+	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x04, prev_ast_cfg);
+	pci_write_config32(PCI_DEV(1, 0x1, 0), 0x14, prev_ast_bar1);
+
+	/* Deconfigure SP5100 PCI bridge */
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x04, prev_sec_cfg);
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x22, prev_sec_mem_limit);
+	pci_write_config16(PCI_DEV(0, 0x14, 4), 0x20, prev_sec_mem_base);
+	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x1a, prev_sec_sub_bus);
+	pci_write_config8(PCI_DEV(0, 0x14, 4), 0x19, prev_sec_bus);
 }

static const uint8_t spd_addr_fam15[] = {