Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56013 )
Change subject: soc/intel/common: Add Intel Power Engine support to discoverable PMC ......................................................................
soc/intel/common: Add Intel Power Engine support to discoverable PMC
In order to get rid of pep.asl, skylake also needs to support runtime generation of the Intel Power Engine, therefore add this support to devices that have a discoverable PMC as well.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed --- M src/soc/intel/common/block/pmc/pmc.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56013/1
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 0ff71b9..e3cab11 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -5,6 +5,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <soc/pci_devs.h>
@@ -73,6 +74,12 @@ pch_pmc_add_io_resources(dev, config); }
+static void pmc_fill_ssdt(const struct device *dev) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) + generate_acpi_power_engine(dev); +} + static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, @@ -80,6 +87,9 @@ .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = pmc_fill_ssdt, +#endif };
static const unsigned short pci_device_ids[] = {